Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Abstract: A comparator circuit for reducing current consumption in a low consumption mode while suppressing the generation of glitches during a transitional period. The comparator circuit includes a comparison core circuit unit, a monitor circuit unit formed by a first transistor, and a nonlinear amplification circuit. The comparison core circuit includes second and third transistors connected to a constant current source. The source terminal and gate terminal of the first transistor have the same connection as the source terminal and gate terminal of the third transistor. The current flowing to the first transistor is supplied to the nonlinear amplification circuit. The nonlinear amplification circuit amplifies the supplied current with an incorporated constant current source and supplies the amplified current to the source terminals of the second and third transistors of the comparison core circuit.

Abstract: A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.

Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.

Abstract: Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.

Abstract: N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: A self-aligning resonator filter, a self-aligning coupled resonator filter circuit, and a television tuner circuit incorporating the filter and the circuit are disclosed herein. The self-aligning resonator filter leverages the local oscillator of the tuner circuit and can be realized with a significant reduction in the amount of off-chip components. The self-aligning resonator filter is configured to align its tunable resonator to resonate at a desired frequency in response to a phase difference measured across a resistance element during a tuning mode, and the resistance element is switched out of the self-aligning resonator filter during a run mode. The self-aligning coupled resonator filter circuit is configured to isolate its individual resonator stages during tuning such that each resonator stage can be aligned without being influenced by the other resonator stage.

Abstract: A system (500) and method (400) are presented for calibrating an analog signal path (200) associated with an Ultra Wideband (UWB) receiver (103). The analog signal path includes a plurality of analog gain stages (210, 212-214, 216), a local oscillator mixer stage (211), a compensation stage (218), and a converter stage (219). A frequency offset of 4 Mhz is applied to a local oscillator signal to reduce a correlation between a received signal and the local oscillator signal. One of the analog gain stages is activated and an offset obtained at the converter stage is stored as a compensation value (243). The compensation value is retrieved whenever the analog gain stages is activated during normal processing and the compensation value applied at the compensation stage to reduce the offset.

Abstract: A low profile integrated module is fabricated to include sheets of material, such as ceramic or PCB, fixed together and including a via extending through at least one of the plurality of sheets from the lower module surface partially to the upper module surface and in a side module surface. The via is filled with conductive material. The module is then mounted on a supporting substrate having a solder pad on the mounting surface with an area greater than the lower surface of the via. The lower surface of the via is positioned adjacent the upper surface of the mounting pad and soldered so that solder wicks up the via along the side module surface.

Abstract: A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Abstract: An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (62); and a metallization feature (70) disposed about and isolated from at least two sides of the top plate (62), the metallization feature (70) for coupling the bottom plate (86,88) to the shield (74). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Abstract: An amplifier is disclosed that contains a transistor (BJT), a switch (MOSFET), and a transformer. The collector of the BJT is connected to an end of the transformer while the base of the BJT is connected to a point between the ends of the transformer through the MOSFET. When the amplifier is in an active mode in which the amplifier has gain, signals supplied to the amplifier are provided to the transformer through the BJT. When the amplifier is in a bypass mode in which the amplifier does not have gain, signals supplied to the amplifier are provided to the transformer through the MOSFET and the BJT is turned off. The amplifier is designed such that the amplifier characteristics are optimized and then the MOSFET is connected to the transformer such that the input impedance of the amplifier is independent of the mode.

Abstract: A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.

Abstract: A tracking circuit (100) is provided for controlling a locally-generated clock. A receive channel (110) in the tracking circuit receives an incoming signal and a local clock, generates a local signal based on the local clock, and compares the local signal and the incoming signal to generate a data signal and an unfiltered phase error signal. A loop filter (120) filters the unfiltered phase error signal to provide a filtered phase error signal. A numerically controlled oscillator (140) generates a correction clock based on the filtered phase error signal. And a filter control circuit (160) provides one or more filter control signals to control operational parameters of the loop filter. The correction clock is provided to the receive channel to modify at least one of the phase and frequency of the local clock. In addition, a sample switch (125) may also be provided to sample the unfiltered phase error signal.

Abstract: A system and method for fast synchronization of an incoming signal with a UWB receiver. The present invention synchronizes a UWB receiver with an incoming signal. The present invention correlates a local pulse generated at the receiver with the incoming signal, finds the value in the correlation function that would correspond to a high signal to noise ratio, thereby matching the receiver to the incoming signal phase, and operates the receiver at that phase. Exemplary options of fast synchronization include a maximum peak detector.

Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Abstract: An ultra-wide band (UWB) waveform receiver with noise cancellation for use in a UWB digital communication system. The UWB receiver uses a two-stage mixing approach to cancel noise and bias in the receiver. Self-jamming is prevented by inverting a portion of the received signal in the first mixer and then coherently detecting the partially and synchronously inverted signal in the second mixer. Since the drive signals on both mixers are not matched to the desired signal, leakage of either drive signal does not jam the desired signal preventing the receiver from detecting and decoding a weak signal.