Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Abstract: Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) and drains coupled respectively to second and third RF I/O ports (118, 120), and gates (136, 138), coupled respectively to first and second control terminals (122, 124). The multi-gate regions (66, 68) of the FETs (50) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (66, 68), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (84).

Abstract: Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

Abstract: A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.

Abstract: An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.

Abstract: A method of recognizing a synchronization message from a wireless telecommunications device comprising the steps of: dividing a series of known identification codes into a plurality of sections; processing and storing the sections of the known identification codes; dividing a signal received from the wireless telecommunications device into a plurality of sections; processing the sections of the received signal; and comparing the sections of the received signal with the sections of the known identification codes.

Abstract: A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units.

Abstract: A circuit (100) is provided for notching an incoming wireless signal. The circuit comprises: a notching mechanism (110) for receiving an incoming signal and generating a notched signal having reduced power at the notch frequency (320), the notch frequency being adjustable in response to a notching control signal; a signal parameter detector (165, 170, 175, 180, 185) for detecting a signal parameter of the notched signal (325); a controller (155) for receiving the signal parameter and for generating the notching control signal (315), the controller being configured to vary the signal parameter within a notching control signal range (340); and a memory (160) for storing the signal parameter and the notching control signal received from the controller in a notching database (330). The controller is configured to analyze the notching database to determine an optimal notching control signal to achieve a desired level of signal performance (345).

Abstract: A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to receiving a memory transaction request associated with the coherency granule at the processor. A coherency state of the coherency granule retained at the processor subsequent to the memory transaction request is determined based on the plurality of coherency states and an indicator representative of the coherency state of the coherency granule retained at the processor is provided for receipt by a cache coherency directory.

Abstract: A level shifter circuit that properly operates even when the power supply voltage is unstable. A level shifter circuit includes a first level shifter unit, a second level shifter unit, and a latch unit. In the first level shifter unit, a transistor is connected to a power supply line to generate drive voltage that is lower than a first power supply voltage. The first level shifter unit outputs complementary signals from the drive voltage. The output of the first level shifter unit is provided to the second level shifter unit. The second level shifter unit converts a complementary signal to a signal having a second power supply voltage. Based on this signal, a signal of the latch unit is switched.

Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

Abstract: A method is provided for transmitting data. A first device (121) generates a first signal (320) having a first duty cycle, comprising a first gated-on portion (323) and a first gated-off portion (363) in a time slot (260); and a second device (125) generates a second signal (330) having second duty cycle, comprising a second gated-on portion (333) and a second gated-off portion (363) in the same time slot (260). The first gated-on portion (323) is generated during a first segment of the time slot (260) and the first gated-off portion (363) is generated during a second segment of the time slot (260), while the second gated-on portion (333) is generated during the second segment and the second gated-off portion (363) is generated during the first segment. The first and second duty cycles are individually below 100%, and the sum of the first and second duty cycles is below 100%.

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

Abstract: A Universal Serial Bus transmitter comprising a USBTXP input and a USBTXM input for receiving respective data signals, and a USBP driver and a USBM driver for applying the respective data signals to USBP and USBM wires respectively. The transmitter comprises a transmit signal generator responsive to an asserting edge of a signal at one of the USBP and USBM inputs to define a leading edge of a transmit signal (USBTXIP) and to a corresponding de-asserting edge of a signal at the other of the USBP and USBM inputs to define the subsequent trailing edge of said transmit signal (USBTXIP). Even if the duty cycles of the input signals USBTXP and USBTXM are substantially different from 50%, this does not cause unacceptable jitter of successive crossover points nor cause the crossover point voltage level to be outside the USB tolerance, centred on 50% of the voltage swings of the USBP and USBM signals.

Abstract: A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway includes a latch that stores the output of the dynamic module. The two output pathways are connected to a logic gate connected to downstream circuitry. Accordingly, data is provided to downstream circuitry rapidly via the first pathway, while being latched to allow the data to be available to the downstream circuitry after the evaluation phase. Such a parallel latching configuration provides enhanced efficiency in transfer and processing of information, especially in conjunction with utilization of precharge and evaluation phases.

Abstract: A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (e.g. 40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module (70) is coupled to each of the plurality of functional circuits (14, 24, 34). The interface module (70) provides control information to the plurality of functional circuits (14, 24, 34) to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module (70) provides a timestamping message from one, several or all time domains at a common interface port (90).

Abstract: Current is provided from a first node coupled to an output of a power supply to a second node coupled to a voltage supply input of an electronic device under test via a transistor having a first current-carrying electrode coupled to the first node and a second current-carrying electrode coupled to the second node. A first voltage is determined based on a voltage difference between the first node and the second node and a second voltage is determined based on a comparison of the first voltage to a voltage of the second node. The transistor is selectively disabled based on the second voltage.

Abstract: A polishing pad can include a first layer and a second layer. The first layer can have a first polishing surface and a first opening. The second layer can have an attaching surface and a second opening substantially contiguous with the first opening. The polishing pad can further include, a pad window lying within the first opening. The pad window can include a second polishing surface. When the pad would be attached to a platen, the first and second polishing surfaces can lie along a same plane, and an opposing surface of the pad window can abut an exterior surface of a platen window. In another aspect, a polishing apparatus can include an exterior surface of a platen window abutting the polishing pad. In still another aspect, a process of polishing can include polishing a workpiece such that the pad window contacts the workpiece and the platen window simultaneously.

Abstract: A method of optimising the operation of a WLAN device which is used in the transmission and reception of a service over a medium, the WLAN device comprising a WLAN chip set and power amplifier, the method comprising the steps of: determining a the value of a collision avoidance metric of the chip set at a specific time; predicting the available bandwidth of the WLAN from the value of the metric; determining the current data rate of the WLAN based on predicted available bandwidth and the type of service; and selecting a power amplifier bias voltage that is the minimum permitted for the determined current data rate to reduce the power consumption of the WLAN device.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.