Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Abstract: A method (300) of extending battery life in a communication device having a plurality of receivers includes receiving information with a primary receiver that is configured to operate on a first network (303) and controlling a secondary receiver that is configured to operate on a second network that is independent from the first network in accordance with the information obtained with the primary receiver. A corresponding communication device (201) includes: a primary receiver (221) configured to operate on a first network (203); a secondary receiver (227, 233) configured and arranged to operate as a short range receiver with an access point (205, 207) that is independent of the first network; and a controller (225, 231, 237) that is configured to control the secondary receiver in accordance with information obtained from the primary receiver.

Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Abstract: A ripple filter circuit for ensuring the driving of a driving subject while efficiently eliminating ripple even when the operational voltage margin is small. A first transistor, which is connected to a power supply voltage line, is connected to a ground line via a load of the driving subject. A second transistor, which has substantially the same characteristics as the first transistor, and a dummy load are arranged between the power supply voltage line and the ground line. An operational amplifier includes an inverting input terminal, connected between the second transistor and the dummy load, and a non-inverting terminal at which the voltage is decreased by a predetermined voltage from the power supply voltage. The operational amplifier also includes an output connected to the gate terminal of the second transistor and to the gate terminal of the first transistor via a lowpass filter.

Abstract: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium.

Abstract: Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.

Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.

Abstract: A method for implementing a Media Independent Handover (MIH) service between one or more of a heterogeneous and a non-heterogeneous network comprises providing an MIH beacon from one or more of a network (Net) or a mobile node (MN); acknowledging a receipt of the MIH beacon by another of the network (Net) or the mobile node; and facilitating handover (HO) services in response to an acknowledged receipt, and further in response to an MIH beacon message subsequently provided from one or more of the network (Net) or the mobile node. In one embodiment, the MIH beacon comprises at least an MIH-Capability (MIHC) flag, the MIHC flag having one of a first state or a second state.

Abstract: A method and a communication device for processing ATM cells. The communication device includes an input interface adapted to receive an ATM cell that is associated with a PHY value and includes a pair of VCI and VPI fields. The communication device is characterized by comprising a search unit, adapted to search, within a group of memory entries that belong to a memory unit, for a pair of VCI and VPI fields that have values that match the values of the VCI and VPI fields of the received ATM cell, if the received VCI field and VPI fields belong to a first predefined group of VCI and VPI fields. The communication device further includes a processor, connected to the search unit, wherein the processor is adapted to determine a channel identifier of the received ATM cell in response to a result of the search and in response to a PHY value associated with the received ATM cell.

Abstract: During processing of a semiconductor wafer bearing a structure including a low-k dielectric layer, a cap layer and the metal-diffusion barrier layer, a chemical mechanical polishing method applied to remove the metal-diffusion barrier material involves two phases. In the second phase of the barrier-CMP method, when the polishing interface is close to the low-k dielectric material, the polishing conditions are changed so as to be highly selective, producing a negligible removal rate of the low-k dielectric material. The polishing conditions can be changed in a number of ways including: changing parameters of the composition of the barrier slurry composition, and mixing an additive into the barrier slurry.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

Abstract: A method is provided for dynamically controlling aggregation in an ultrawide bandwidth wireless device. In this method, a device receives a plurality of intermediate service data units at an intermediate layer, aggregates at least two of the plurality off intermediate service data units to form an intermediate protocol data unit, and sends the intermediate protocol data unit to a physical layer. The physical layer generates a data frame based on the intermediate protocol data unit and information corresponding to the physical layer, and transmits the data frame in a data stream. The device selects an intermediate size criteria for the intermediate protocol data unit based on a desired frame size criteria for the data frame. The aggregating of the at least two of the plurality of intermediate layer service data units is performed such that an actual intermediate layer protocol data unit size corresponds to the intermediate size criteria.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

Abstract: Embodiments of the present invention relate generally to digital volume control in digital audio systems. One embodiment relates to a digital audio system having a digital audio processor and a digital volume control coupled to the digital audio processor. The digital volume control includes a feedback loop having an attenuator, and error determination unit, and a filter. The feedback loop determines the attenuation error and shifts the attenuation error beyond a predetermined digital audio range. The output of the digital volume control maintains a substantially constant SNR and THD with respect to the level attenuation over the predetermined digital audio range.

Abstract: A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.

Abstract: A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack including a control gate (111) and a layer of memory material (113). A source/drain region (123) is then formed between the first and second sets of memory stacks, and a silicide layer (125) is formed over the source/drain region.

Abstract: A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity shapes, and top gate contact shapes, bottom gate contact shapes, thru-gate contact shapes, and source/drain contact shapes for the planar double gate transistors. The method can generate gate contact shapes that have top and bottom gates to be electrically connected within the same planar double gate transistor or separate gate contact shapes where the top and bottom gates are not electrically connected to each other. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.