Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a state of the first word line and a state of the second word line. The memory device further comprises control logic to configure, for an access to the bit cell, the state of the first word line and the state of the second word line based on an access type of the access.

Abstract: A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).

Abstract: A method (800) is provided of processing a wireless signal (105) at a receiving device (125). The method includes: receiving the wireless signal at the receiving device; performing an acquisition process (820, 830) to determine a phase estimate for the wireless signal; adjusting the phase estimate by a correction value (840) after performing the acquisition process; and performing a tracking process (860) to maintain accuracy in the phase estimate, after adjusting the phase estimate.

Abstract: A processing system includes a direct current to direct current (DC-DC) converter for generating a supply voltage when coupled to a battery. A memory module stores a plurality of operational instructions. A processing module receives power from the DC-DC converter and executes the plurality of operational instructions. A power monitor circuit monitors the power source and powers down the power source when a first error condition is detected in the power source.

Abstract: Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages (300, 400) down to chip-scale packages. Such QFN packages include a first semiconductor chip (310, 410), a plurality of recessed leads (306, 406, 408, 411) having mold lock features, and a mold material 340, 440 substantially encasing all sides of the semiconductor chip. An active surface (314, 414) of the semiconductor chip is oriented toward a mounting side (307, 407) of the QFN package, and a plurality of wire bonds 330, 430 disposed between the active surface and the mounting side couple the active side to the leads. The QFN packages may also include a second semiconductor chip (452) coupled to a plurality of leads (408) and to the first semiconductor chip via wire bonds (431, 432) in a manner similar to the first semiconductor chip.

Abstract: A transducer (20) includes a movable element (24), a self-test actuator (22), and a sensing element (56, 58). The sensing element (56, 58) detects movement of the movable element (24) from a first position (96) to a second position (102) along an axis perpendicular to a plane of the sensing element (56, 58). The second position (102) results in an output signal (82) that simulates a free fall condition. A method (92) for testing a protection feature of a device (70) having the transducer (20) entails moving the movable element (24) to the first position (102) to produce a negative gravitational force detectable at the sensing element (56, 68), applying a signal (88) to the actuator (22) to move the movable element (24) to the second position (102) by the electrostatic force (100) , and ascertaining an enablement of the protection feature in response to the simulated free fall.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A device includes an anti-fuse including a first electrode that can be selectively coupled to a first voltage reference and a second electrode that can be selectively coupled to a second voltage reference. The device further includes a shunt transistor including a first current electrode coupled to the first electrode of the anti-fuse, a second current electrode coupled to the second electrode of the anti-fuse, and a control electrode. The device additionally includes control logic configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse.

Abstract: A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current.

Abstract: Dynamic gain and phase compensation is provided in a radio frequency (RF) receiver (106) including at least one switched Low Noise Amplifier (LNA) (212) coupled to an RF gain control unit (226) providing a gain control signal to the at least one switched LNA (212) for control thereof. The RF receiver also includes an analog-to-digital (A/D) converter (222) for digitizing the RF signal and outputting an N-bit digital signal to the RF gain control unit (226). The method for gain compensation includes dynamically adjusting the N-bit digital signal to compensate for the at least one switched LNA (212) in response to the gain control signal. The method for phase compensation includes dynamically normalizing the N-bit digital signal into an M-bit signal range to derive an M-bit digital signal, where M?N and dynamically phase adjusting the M-bit digital signal to compensate for the at least one switched LNA (212) in response to the gain control signal.

Abstract: A controllable oscillator includes an output oscillation adjust module operably coupled to an oscillator for producing an effective output oscillation based on an oscillation control signal. The output oscillation adjust module includes an output select block that produces the effective output oscillation from a sequence of selected taps from the plurality of taps of the oscillator. A tap adjust control generator, responsive to the oscillation control signal generates a sequence of tap adjust control signals that command the output select block to select the sequence of selected taps from the plurality of taps. The tap adjust control generator includes an integrator having an integrator output, responsive to the oscillation control signal and a modulo(x) module for producing the sequence of tap adjust control signals based on the integrator output.

Abstract: An electronic apparatus and a method of conserving energy comprises providing an energy-conservation module to control use of one or more energy-saving mechanism by a hardware element. The energy-conservation module comprises a performance estimation module that estimates a performance level requirement of the hardware element and a slack time. A cost-benefit qualifier module is provided that uses one or more generic algorithm and at least one separate record that characterises power use and performance by the hardware element in relation to a Performance Power state of the selected energy-saving mechanism in order to determine an existence of an energy saving. The cost-benefit qualifier module sets the hardware element to use the Performance Power state of the selected energy-saving mechanism if the energy-saving exists.

Abstract: A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage.

Abstract: An integrated circuit comprising an adjustable voltage source to allow a plurality of voltage values to be selected; means for measuring a voltage value derived from the adjustable voltage source; and means for configuring the adjustable voltage source to provide a selected voltage value, wherein the selected voltage value is selected based upon a voltage value measured by the means for measuring and a voltage selected by a controller.

Abstract: A semiconductor integrated circuit for intentionally and flexibly changing a monitoring subject bit if debugging is performed during software processing when a status change occurs. A replacement data register and a comparison address register, which are settable from a microprocessor, determine matching of an address input from the microprocessor and a comparison address value. When the addresses match in a test mode, instead of outputting normal status data, a predetermined value of the replacement data register is output in response to a read request from the microprocessor.

Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: Power supply apparatus, especially for the active circuits of a portable radio communication device. The power supply supplies a direct voltage to a load that is connected to a first terminal, is comprising a rechargeable battery for connection to a second terminal, and a voltage generator for recharging the battery and supplying power to the load. The power supply includes first control means for controlledly supplying current from the voltage generator to the first terminal so as to control supply of current from the voltage generator to the load and for preventing reverse flow of current from the first terminal to the voltage generator, and second control means for controlledly supplying current between the first and second terminals so as to control supply of current from the voltage generator through the first control means to the battery and from the battery to the load.