Patents Assigned to Freescale
  • Integrated circuit with multiplexed I/O pads
    Patent number: 9385690
    Abstract: An integrated circuit (IC) includes power domains and I/O multiplexing units. The I/O multiplexing units include components that are spilt across the power domains. The I/O multiplexing units multiplex signals received from the power domains and provide signals to one or more peripheral devices connected to the IC by way of I/O pads of the IC.
    Type: Grant
    Filed: August 9, 2015
    Date of Patent: July 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Neha Agarwal, Mayank Agrawal, Chandan Gupta, Saurinkumar Patel, Victor Zamanski
  • Real-space charge-transfer device and method thereof
    Patent number: 9385321
    Abstract: A real-space charge-transfer device is disclosed. In particular, a Gunn diode is disclosed having a conductive structure fabricated overlying its active region. A secondary signal, other than the normal Gunn diode signal, is generated by the Gunn diode based upon a characteristic of the overlying conductive structure. For example, when the conductive structure is a grate having N teeth the secondary signal will have N secondary oscillation cycles that occur during the duration of a single normal Gunn diode oscillation cycle.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Don D. Smith
  • Integrated circuit with multi-voltage input/output (I/O) cells
    Patent number: 9383794
    Abstract: An integrated circuit (IC) includes a first I/O cell, a logic cell, a trigger signal generation circuit, and a second I/O cell having a voltage selection pin. I/O interfaces of the first I/O cell receive first and second supply voltages, respectively, and I/O interfaces of the second I/O cell receive third and fourth supply voltages, respectively. The first I/O cell generates a first trigger signal when the first supply voltage reaches a first predetermined voltage. The logic cell receives the first trigger signal and generates a safe-state signal. The trigger signal generation circuit generates a second trigger signal when the third supply voltage reaches a second predetermined voltage. The voltage selection pin receives the safe-state signal and the second trigger signal and sets the second I/O cell in a safe-state mode, which protects the second I/O cell from over voltage damage.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: July 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Aggarwal, Rohit Gupta, Ashish Malhotra, Andrey Malkov, Evgeny A. Shevchenko
  • Heat sink having a through-opening
    Patent number: 9385064
    Abstract: A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Trent S. Uehling
  • Semiconductor device with improved breakdown voltage
    Patent number: 9385229
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Virtualized local storage
    Patent number: 9384153
    Abstract: Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas E. Tkacik, Charles E. Cannon, Carlin R. Covey, David H. Hartley, Rodney D. Ziolowski
  • Open loop band gap reference voltage generator
    Patent number: 9385689
    Abstract: A reference voltage generator that does not require a start-up circuit or a feedback loop generates a proportional-to-absolute-temperature (PTAT) output voltage based on two complementary-to-absolute-temperature (CTAT) currents. The reference voltage generator provides a reference voltage that is a sum of the PTAT output voltage and a CTAT voltage.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: July 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nishant Singh Thakur, Pralay Mandal
  • SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A PACK-INSERT OPERATION
    Publication number: 20160188331
    Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.
    Type: Application
    Filed: June 18, 2013
    Publication date: June 30, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Avi GAL, Fabrice AIDAN, Noam ESHEL-GOLDMAN, Roy GLASNER, Dmitry LACHOVER, Itay PELED
  • Method and apparatus for performing integrated circuit layout verification
    Patent number: 9378325
    Abstract: A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xavier Hours, Shitiz Arora, Robert Scott Ruth
  • Integrated circuit interconnect crack monitor circuit
    Patent number: 9377504
    Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stanley A. Cejka, Steven A. Atherton, William J. Downey, James C. Golab, Brian D. Young
  • Dual-voltage detector having disable outputs within separate voltage domain and related methods
    Patent number: 9379700
    Abstract: Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Dzung T. Tran, Trong D. Nguyen
  • Capacitive arrangement for frequency synthesizers
    Patent number: 9379721
    Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cristian Pavao-Moreira, Dominique Delbecq, Jean-Stephane Vigier
  • Microelectronic packages having stacked accelerometer and magnetometer die and methods for the production thereof
    Patent number: 9376310
    Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Non-volatile memory using bi-directional resistive elements
    Patent number: 9378812
    Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Frank K. Baker, Jr.
  • IC package having non-horizontal die pad and lead frame therefor
    Patent number: 9379035
    Abstract: A multi-component integrated circuit (IC) package has a base component (e.g., an interposer) defining a base of the IC package, a plurality of die pads extending from the base and forming side walls of the IC package, one or more IC dies, each mounted on an interior surface of one of the die pads, and bond wires electrically connecting the IC dies to another component of the IC package, such as the interposer or another die. By mounting dies on non-horizontal side walls, the IC package can provide more-effective thermal dissipation than conventional 3D IC packages having stacks of IC dies.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: You Ge, Meng Kong Lye, Zhijie Wang
  • Timing event generation circuit for wireless communication apparatus
    Patent number: 9380473
    Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Somvir Dahiya, Nikhil Jain, Rajan Kapoor
  • Method of making a split gate non-volatile memory (NVM) cell
    Patent number: 9379222
    Abstract: Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko
  • REAL-SPACE CHARGE-TRANSFER DEVICE AND METHOD THEREOF
    Publication number: 20160181523
    Abstract: A real-space charge-transfer device is disclosed. In particular, a Gunn diode is disclosed having a conductive structure fabricated overlying its active region. A secondary signal, other than the normal Gunn diode signal, is generated by the Gunn diode based upon a characteristic of the overlying conductive structure. For example, when the conductive structure is a grate having N teeth the secondary signal will have N secondary oscillation cycles that occur during the duration of a single normal Gunn diode oscillation cycle.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Don D. Smith
  • SEMICONDUCTOR WAFER AND METHOD OF FABRICATING AN IC DIE
    Publication number: 20160180891
    Abstract: There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: ROBERT F. MORAN, DEREK BEATTIE, MARK MAIOLANI
  • SEMICONDUCTOR DEVICES AND RELATED FABRICATION METHODS
    Publication number: 20160181421
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 23, 2016
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: HONGNING YANG, DANIEL J. BLOMBERG, XIN LIN, ZHIHONG ZHANG, JIANG-KAI ZUO