Patents Assigned to Fuji Electric Holdings Co., Ltd.
  • Patent number: 7407837
    Abstract: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: August 5, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Takashi Tsuji
  • Publication number: 20080153212
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Application
    Filed: February 4, 2008
    Publication date: June 26, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Manabu TAKEI
  • Patent number: 7381504
    Abstract: A method and apparatus for manufacturing a color conversion filter. The method includes forming a color filter layer on a transparent substrate. A coloring matter layer containing color conversion coloring matter and an optical radical generating agent are formed on the substrate and the filter layer. The coloring matter layer is exposed to coloring matter decomposition light applied through the substrate and the filter layer. The coloring matter layer also is exposed to auxiliary ultraviolet light applied from the side of the coloring matter layer. This forms a color conversion layer at a position corresponding to the filter layer. The optical radical generating agent is heat vaporized. The color conversion coloring matter is decomposed by light whose wavelength is outside a range that the color filter layer transmits. The coloring matter decomposition light includes a wavelength component that decomposes the color conversion coloring matter.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: June 3, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Koji Kawaguchi, Makoto Kobayashi, Kenya Sakurai
  • Publication number: 20080108270
    Abstract: A method of manufacturing a white light emitting organic EL device is disclosed. A white light emitting organic EL device having a plurality of organic EL layers each emitting different color light from each other without an increase in a driving voltage is readily fabricated. The method manufactures a white light emitting organic EL device having at least a reflective electrode, a first organic EL layer that emits light in a first color, an intermediate electrode unit, a second organic EL layer that emits light in a second color different from the first color, and a second transparent electrode in this order. The reflective electrode is of the same polarity as the second transparent electrode, and the intermediate electrode unit is of opposite polarity to the reflective electrode and the second transparent electrode.
    Type: Application
    Filed: October 22, 2007
    Publication date: May 8, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Toshio HAMA
  • Patent number: 7368799
    Abstract: The semiconductor apparatus is disclosed that includes a partial SOI substrate including an oxide film; a lateral first MOSFET section having a planar gate structure and formed in the portion of the partial SOI substrate where there is an oxide film; a vertical second MOSFET section having a trench gate structure and formed in the portion of the partial SOI substrate where there is no oxide film, the second MOSFET section being adjacent to the first MOSFET section. The first MOSFET section includes a first p-type base region on the oxide film. The second MOSFET section includes a second n+-type drain region, a second n-type drift region on the second n+-type drain region, and a second p-type base region in the surface portion of the second n-type drift region.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: May 6, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Tatsuji Nagaoka
  • Patent number: 7358127
    Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: April 15, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Michio Nemoto
  • Patent number: 7355257
    Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 8, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno
  • Patent number: 7355263
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 8, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20080079008
    Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 3, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Yoshiyuki YONEZAWA, Takeshi TAWARA
  • Publication number: 20080081389
    Abstract: A transparent first substrate and a second substrate of an organic multicolor emission and display device are positioned opposite to each other with a predetermined clearance and sealed with a gap material that performs desiccating a surrounding atmosphere. The gap material advantageously has different void fractions between in an inner portion facing a sealed space within the device and in an outer portion facing an external atmosphere. Featuring the above structure, an organic multicolor emission and display device of color conversion system has been provided that maintains stable light emitting performance for a long period and exhibits excellent visibility angle characteristic.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 3, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Noriyuki MATSUKAZE
  • Publication number: 20080062578
    Abstract: A spin injection magnetization reversal device is disclosed which inhibits an increase in resistance to enable multi-valued data recording. A ferromagnetic fixed layer and n groups each including a ferromagnetic free layer and an isolation layer are disclosed. The groups are disposed from the group including the first ferromagnetic free layer provided on the ferromagnetic fixed layer to the group including the n-th ferromagnetic free layer in the order. Each of the ferromagnetic free layers is preferably formed of one of a CoCrPt alloy, a CoCr alloy and a CoPt alloy with Pt or Cu concentration therein made monotonically decreased from the concentration in the first ferromagnetic free layer to that in the n-th ferromagnetic free layer.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 13, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Hideaki WATANABE, Akira SAITO
  • Patent number: 7338887
    Abstract: A method that controls the distribution of plasma generated in a vacuum chamber, for example, as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions. The vacuum chamber includes a high-frequency-wave electrode connected to a high-frequency electric power supply and an earth electrode connected to ground potential. High frequency-electric power is fed to the high-frequency-wave electrode and peak-to peak voltages are measured at multiple measuring points on one of the two electrodes. The distribution of the plasma is controlled by adjusting the chamber pressure to minimize the differences between the measured peak-to-peak voltages.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: March 4, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Makoto Shimosawa
  • Publication number: 20080045038
    Abstract: A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region, and has a surface configuration including raised parts. A first dummy pattern is formed in a region between the peripheral ring electrode and the device element on the substrate.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 21, 2008
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Takayuki Hirose, Masaharu Edo, Akira Sato
  • Publication number: 20080044773
    Abstract: A method of manufacturing a color conversion layer with a predetermined pattern is disclosed which does not cause any damage on the color conversion layer formed by a dry process such as an evaporation method to achieve a large scale and high definition. The method includes steps of sequentially forming, on a substrate, an etch stop layer, a color conversion layer by means of an evaporation method, a protective layer and a transparent mask layer; patterning a resist layer formed on the transparent mask layer to have a predetermined pattern; transferring the pattern from the resist layer to the transparent mask layer using the patterned resist layer as a mask; removing the patterned resist layer; and dry etching, using the patterned transparent mask layer as a mask, to transfer the pattern to the protective layer and the color conversion layer.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 21, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Yukinori KAWAMURA
  • Publication number: 20080012026
    Abstract: A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device and method for manufacturing the same allow a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 17, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Takashi Tsuji
  • Publication number: 20080003455
    Abstract: A white organic EL element structure exhibiting a good emission efficiency in which the emission color does not vary with current application time. The organic EL element has an organic EL layer sandwiched by a pair of electrodes, characterized in that wherein the organic EL layer includes at least a carrier recombination layer and one or more of carrier nonrecombination layers the carrier recombination layer emits blue or blue green EL light having a peak wavelength of 400-500 nm through recombination of carriers injected into the organic EL element, the carrier nonrecombination layer contains a host material having carrier injection/transportation ability and absorbing at least a part of the EL light and one or more of kinds of PL emission dye material emitting PL light of lower energy than that of the EL light, and the distance between the carrier recombination layer and the carrier nonrecombination layer is 15 nm or above.
    Type: Application
    Filed: October 20, 2005
    Publication date: January 3, 2008
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Chong Li, Hiroshi Kimura, Koji Kawaguchi, Yutaka Terao, Toshio Hama
  • Patent number: 7312133
    Abstract: A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: December 25, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Akio Kitamura
  • Publication number: 20070290612
    Abstract: [Problems] To provide a white or multicolor light emitting device that sufficiently contains components of various wavelength regions while having excellent brightness balance among the colors, and a method for producing such a light emitting device by a simple process. [Means to Solve the Problems] A light emitting device comprising, on a transparent substrate, a complementary color layer, a transparent electrode, an organic light emitting body and a reflective electrode. This light emitting device is characterized in that the organic light emitting body comprises at least a blue light emitting layer and a red light emitting layer, the complementary color layer absorbs a part of the light emitted from the organic light emitting body and emits green light, and the device emits white light from the transparent substrate side.
    Type: Application
    Filed: September 6, 2005
    Publication date: December 20, 2007
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Toshio Hama, Koji Kawaguchi, Makoto Kobayashi, Kenya Sakurai
  • Publication number: 20070292995
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Michio NEMOTO, Manabu TAKEI, Tatsuya NAITO
  • Publication number: 20070290267
    Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: Fuji Electric Holdings Co., Ltd
    Inventors: Koh Yoshikawa, Setsuko Wakimoto, Hitoshi Kuribayashi