Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract: A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

Abstract: The disclosed technology generally relates to photovoltaic devices and methods of fabricating photovoltaic devices, and more particularly relates to interdigitated back contact photovoltaic cells and methods of fabricating the same. In one aspect, a method of forming first and second interdigitated electrodes on a semiconductor substrate comprises providing a dielectric layer on the rear surface of the semiconductor substrate. The method additionally comprises providing a metal seed layer on the dielectric layer. The method additionally comprises patterning the metal seed layer by laser ablation, thereby separating it into a first seed layer and a second seed layer with a separation region interposed therebetween, wherein the first seed layer and the second seed layer are interdigitated and electrically isolated from each other. The method further comprises thickening the first seed layer and the second seed layer by plating, thereby forming the first electrode and the second electrode.

Abstract: A stretchable electronic device is disclosed. In one aspect, the device includes at least one combination of a stretchable electronic structure having a first Young's modulus and a rigid or flexible electronic structure having a second Young's modulus higher than the first Young's modulus. The stretchable electronic structure and the rigid or flexible electronic structure may be electrically connected to each other by a semi-transition structure having a third Young's modulus with a value in a range between the first and the second Young's modulus.

Abstract: The present disclosure relates to a direct digital radio frequency modulator that includes a plurality of input terminals arranged to receive a multi-bit digital signal, and a plurality of converter circuits. In one example, the converter circuits are arranged to receive at an input terminal one bit of the multi-bit digital signal and to provide at a converter circuit output terminal an analog signal in accordance to the one bit. In the present example, a converter circuit includes an input transistor arranged to receive the one bit for enabling the converter circuit to produce the analog signal, a current source transistor, an additional transistor in cascode to the current source transistor, and a frequency modulator output terminal connected to the output terminal of each converter circuit for providing an analog output signal.

Abstract: The present disclosure relates to a method for integrating a sub-micron III-V waveguide laser on a semiconductor photonics platform as well as to a corresponding device/system. The method comprises providing on a semiconductor substrate an electrically insulating layer, etching a trench having a width in the range between 50 nm and 800 nm through the electrically insulating layer, thereby locally exposing the silicon substrate, providing a III-V layer stack in the trench by local epitaxial growth to form a channel waveguide, and providing a light confinement element for confining radiation in the local-epitaxial-grown channel waveguide.

Abstract: Methods and systems for measuring capacitance difference are disclosed. In one aspect, first and second capacitive elements are connected between voltage receiving nodes for receiving first and second DC voltages and nodes connectable to a third DC voltage via a first, resp. second switch. Further, in a first phase, a voltage difference is applied to charge the capacitive elements and the switches are alternately closed. First resulting currents are measured. Further, in a second phase, the first and second DC voltages are applied alternatingly and the switches are alternately closed. Second resulting currents are measured. The capacitance difference can be determined from the first and second resulting currents.

Abstract: The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.

Abstract: A method and apparatus is provided for self-assembly of micro-components such as microchips onto a carrier substrate, provided with assembly locations for the components. The components are supplied to the carrier by a liquid flow, while a template substrate is arranged facing the carrier. The template is a substrate provided with openings aligned to the assembly locations. The carrier and template are submerged into a tank filled with the liquid, while the liquid flow is supplied to the template side together with the components, so that the components are guided towards the openings by the flow of liquid. Once a component is trapped into an opening of the template, substantially no further liquid flow through the opening is possible, so that following components are guided towards the remaining openings, thereby establishing a fast and reliable self-assembly process.

Abstract: A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.

Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.

Abstract: The disclosed technology relates generally to photovoltaic cells, and more particularly to photovoltaic cells with plated metal contacts. In one aspect, a method of fabricating a photovoltaic cell with a metal contact pattern on a surface of a semiconductor substrate includes locally smoothening portions of the surface of the semiconductor substrate by using a first laser, at predetermined locations. The method additionally includes doping the surface of the semiconductor substrate to form an emitter region. The method additionally includes forming a dielectric layer on the surface of the semiconductor substrate, and subsequently forming openings through the dielectric layer by using a second laser, thereby locally exposing the underlying surface of the semiconductor substrate at the predetermined locations. The method further includes forming metal contacts at exposed regions of the surface of the semiconductor substrate by plating.

Abstract: A vibration power generator comprises: a fixed substrate; a vibrating body having a surface opposed to the fixed substrate, the vibrating body being vibratable to the fixed substrate; electret electrodes aligned in a vibration direction on one of the surface of the fixed substrate and the surface of the vibrating body; and first fixed electrodes and second fixed electrodes alternately aligned in the vibration direction on the other thereof, wherein when the vibrating body is at a resting position, each of the electret electrodes overlaps with both electrodes of a corresponding fixed electrode pair, the corresponding fixed electrode pair being one of the first fixed electrodes and one of the second fixed electrodes that are opposed to the electret electrode, and when the vibrating body is not at a resting position, each of the electret electrodes always overlaps with at least one electrode of the corresponding fixed electrode pair.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device is disclosed, comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the cation supply electrode consists of a CuxZyeTez alloy with Z being Ge or Si and with y>15 at. %.

Abstract: A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an (N+1) bit code representation for a comparison result, the (N+1) bit code yielding the N bit output signal. On detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for a most significant bit of the (N+1) bit code by replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal, performing an additional comparison cycle using the alternative (N+1) bit code, determining, using comparison results of the additional comparison cycle and the preceding (N+1)th cycle, a sign of a DAC capacitor mismatch error, and tuning programmable binary scaled calibration capacitors in parallel to a capacitor corresponding to the one of the most significant bits of the (N+1) bit code.

Abstract: Composite electrodes are disclosed that comprise an active electrode material and a solid electrolyte, wherein the solid electrolyte is a composite electrolyte. The composite electrolyte comprises an electrically insulating material having a plurality of pores and a solid electrolyte material covering inner surfaces of the plurality of pores. The active electrode material may comprise a plurality of active electrode material particles in electrical contact with each other, and the composite electrolyte may be located in spaces between the plurality of active electrode material particles. The present disclosure is further related to solid-state batteries comprising a stack of an anode, a solid electrolyte layer, and a cathode, wherein at least one of the anode and the cathode is a composite electrode according to the present disclosure. The present disclosure further provides methods for fabricating such composite electrodes and solid-state batteries.

Abstract: An integrated avalanche photodetector and a method for fabrication thereof. The integrated avalanche photodetector comprises a Ge body adapted to conduct an optical mode. The Ge body comprises a first p-doped region that extends from a first main surface to a second main surface of the Ge body. The Ge body further comprises a first n-doped region that extends from the first main surface towards the second main surface of the Ge body. An intrinsic region occupies the undoped part of the Ge body. A first avalanche junction is formed by the first n-doped region that is located aside the p-doped region. The Ge body further comprises an incidence surface, suitable for receiving an optical mode, and a second n-doped Ge region that covers the Ge body and forms a second avalanche junction with the first p-doped region at the first main surface.

Abstract: A current generator is disclosed. An example current generator includes a plurality of current cells connected in parallel, each current cell being connected to a switch. The current generator further includes a first summer configured to sum the output of each current cell of a first subset of the plurality of current cells and a second summer configured to sum the output of each current cell of a second subset of the plurality of current cells. The current generator also includes a combiner configured to combine the outputs of the first and second summers. Further, each switch is switchable according to a sequence to generate a summed output of the current cells at a plurality of quantization levels to generate positive and/or negative alternations of a pseudo-sinusoidal, alternating current.

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract: An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.