Abstract: According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon (SOC) layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass (SOG) layer; subjecting the semiconductor structure to an ion implantation process wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed wherein the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial la

Abstract: A group III-N lateral Schottky diode is disclosed. The diode may include a substrate, a nucleation layer formed on the substrate, a buffer layer formed on the nucleation layer, and a group III-N channel stack formed on the buffer layer. The diode may further include, on the channel stack, a group III-N barrier containing aluminum, where the aluminum content of the barrier decreases towards the channel stack. The diode may further include a passivation layer formed on the group III-N barrier, a cathode formed in an opening through the passivation layer where the opening at least extends to the barrier, and an anode formed in another opening through the passivation layer partially extending into the barrier, the anode forming a Schottky contact with the barrier.

Abstract: The present invention relates to a method for decreasing the impedance of a titanium nitride element for use in an electrode component. The method comprises obtaining a titanium nitride element and hydrothermally treating the titanium nitride element by immersing the titanium nitride element in a liquid comprising water while heating said liquid.

Abstract: The present invention is related to a method and apparatus for cleaning a substrate, in particular a semiconductor substrate such as a silicon wafer. The substrate is placed in a tank containing a cleaning liquid, at an angle with respect to acoustic waves produced in said liquid. The angle corresponds to the angle of transmission, i.e. the angle at which waves are not reflected off the substrate surface. A damping material is provided in the tank, arranged to absorb substantially all waves thus transmitted through the substrate. A significant improvement in terms of cleaning efficiency is obtained by the method of the invention.

Abstract: The present disclosure relates to a modulation circuit and a method for suppressing energy content of spectral side lobes caused by high-frequency content present in a baseband signal, with the energy content of the spectral side lobes being outside an intended operational bandwidth in a modulated radio-frequency signal. An example circuit is configured to: receive a digital baseband signal, feed the digital baseband signal to a first and a second signal path, with the first signal path comprising a first mixer and the second signal path comprising a delay circuit and a second mixer. The first mixer and the second mixer may receive a same local oscillator signal, and may respectively provide a first radio-frequency signal and a second radio-frequency signal that are delayed with respect to each other. The example circuit is further configured to generate an output radio-frequency signal by combining the first and second radio-frequency signals.

Abstract: A biopotential signal acquisition system including an analog readout unit configured to receive an analog biopotential signal, which may be acquired from at least one electrode attached to a body; and to extract an analog measured biopotential signal and an analog reference signal. The system also includes an ADC unit configured to provide a digital version of the analog measured biopotential signal and the analog reference signal, a digital filter unit configured to calculate a digital motion artifact estimate based on the digital version of the measured biopotential signal and the reference signal. The system further comprises a reference signal processing unit configured to convert the reference signal into a new reference signal being provided to the digital filter unit based on the correlation between the measured biopotential signal and the reference signal.

Abstract: An electrode for biopotential sensing comprising a main electrode base and at least a plurality of contact pins protruding from the main electrode base and configured to make contact with a subject's skin. Each of the first plurality of contact pins comprises at least one conductive mesh having an elongated pillar shape. A headset or biopotential monitoring system comprising such an electrode for biopotential sensing.

Abstract: A miniature integrated CMOS sensor circuit comprising a time domain ADC module, a digital logic and control module, a data transmitter module, a power circuit module, a voltage reference module, an identification code tag, and an RF coil disposed within an area of less than 0.1 mm2.

Abstract: A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.

Abstract: The present disclosure relates to a method of managing the operation of a digital synchronous electronic system with a guaranteed lifetime, using digital processing means. The method comprises: monitoring the electronic system at run time, while the electronic system executes a set of application tasks currently running on the electronic system in a current system working mode; detecting a violation in at least one parameter of the electronic system, the violation affecting one or more guaranteed objectives or one or more cost functions; selecting at least one condition to revise the current system working mode of the electronic system; and based on the at least one condition, selecting a revised system working mode to continue execution of the set of application tasks.

Abstract: An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.

Abstract: A method is provided for in-situ monitoring of etch uniformity during plasma etching, on the basis of the detection of interferometry patterns. The method is applicable to a reactor wherein a plasma is created in the area between the surface to be etched and a counter-surface arranged essentially parallel to the surface to be etched. The occurrence of interference patterns is detected at a location that is placed laterally with respect to the area between the surface to be etched and the counter-surface. The presence of an interference pattern at a particular wavelength is observed through the detection of oscillations of the light intensity measured by an optical detector, preferably by the standard Optical Emission Spectrometry tool of the reactor. When these oscillations are no longer detectable, non-uniformity exceeds a pre-defined limit. The counter surface is arranged such that the oscillations are detected.

Abstract: The present disclosure relates to a biosensor device for detecting a predetermined target analyte. The device comprises a substrate. An aptamer bioreceptor for specifically binding to the predetermined target analyte is exposed at a functionalized surface of the substrate. The device also comprises a heat source for heating the substrate via a back surface thereof. The device further comprises a first temperature sensing element for sensing a temperature at the back side of the substrate and a second temperature sensing element for sensing a temperature at the functionalized side of the substrate. The device also comprises a signal processing unit for calculating a heat transfer resistivity value based on temperature values obtained from the first and the second temperature sensing element and the heating power generated by the heat source.

Abstract: An ion sensor for sensing an ion concentration in a bulk solution comprises a reference electrode embedded in an reference electrolyte solution, and a first ion-selective electrode. The ion sensor moreover comprises a second electrode sensitive to the reference ions or to an ion different from the ion to be measured, whereby the second electrode is in direct contact with the bulk solution when the ion sensor is immersed therein. The potential difference between the first electrode and the reference electrode is a measure for the ion concentration in the bulk solution and is corrected with the potential difference between the second electrode and the reference electrode to compensate for the drift of the reference electrode.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity ? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Abstract: A tunable impedance network includes at least one variable impedance bank comprising a plurality of digitally controlled unit cells each connected from at least a first end to a routing wire. The tunable impedance network is provided with selection means arranged for selecting, based on a desired impedance, a corresponding predetermined digital control signal to be supplied to the variable impedance bank to switch-on a corresponding combination of the unit cells. Between each pair of unit cells in the variable impedance bank, a routing wire section is provided having a respective routing impedance. Each of the predetermined digital control signals is provided for switching-on a combination of unit cells in such a way that the routing impedance of the routing wire section is exploited to fine-tune the actual impedance generated by the variable impedance bank.

Abstract: A method for creating a pattern on a substrate (101) is presented, the method comprises: providing a substrate (101) comprising silicon; creating a sacrificial layer (102) on the substrate (101), wherein the sacrificial layer is formed on a first surface area (101a) of the substrate thereby leaving a second surface area (101b) exposed; depositing a first functional layer (103) at least on the second surface area (101b) of the substrate (101); removing the sacrificial layer (102); wherein: removing the sacrificial layer (102) is performed by etching the sacrificial layer (102) with an acidic aqueous solution that does not adversely affect the first functional layer (103) and the substrate (101).

Abstract: An electronic system for estimating a subject's blood pressure, comprising a feature extraction module configured for receiving a subject's photoplethysmogram signal, detecting a plurality of signal characteristic points on the received photoplethysmogram signal, calculating a plurality of distances in both time and amplitude between any two of the detected photoplethysmogram signal characteristic points, and providing a feature information signal comprising information about the calculated distances; and a blood pressure calculation module configured for receiving the photoplethysmogram signal, the feature information signal and anthropometric characteristics of the subject, and calculating systolic, diastolic and continuous mean blood pressure values of the subject.

Abstract: A method for fabricating an integrated semiconductor photonics device is disclosed. The method may include providing a first substrate having on its top surface a monocrystalline semiconductor layer suitable for supporting an optical mode and forming a homogenous and conformal first dielectric layer on a planar surface of the monocrystalline semiconductor layer. The method may further include providing a dielectric waveguide core on the first dielectric layer, the dielectric waveguide core optically coupled to a first region of the monocrystalline semiconductor layer through the first dielectric layer. The method may further include depositing a second dielectric layer on the dielectric waveguide core, thereby covering the dielectric waveguide core, and annealing the substrate to drive hydrogen out of the dielectric waveguide core.

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.