Abstract: A spectroscopy system includes detectors configured to obtain detection spectrums of respective detection areas that are located at different positions of an object; and an information processor configured to obtain a target spectrum of a target area by using position information of the detection areas and the detection spectrums obtained by the detectors.

Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.

Abstract: The disclosed technology generally relates photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions.

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract: A biopotential signal acquisition system comprising an analog readout unit configured to receive an analog biopotential signal and to extract an analog measured biopotential signal and an analog reference signal, and an ADC unit configured to provide a digital version of the analog measured biopotential signal and the analog reference signal. The system also includes a first digital filter unit comprising a cascaded integrator-comb filter configured to provide a first digital filtered version of the digital measured biopotential signal and the reference signal, and a second digital filter unit configured to calculate a digital motion artifact estimate based on the first digital filtered version signals.

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Abstract: An oscillator device comprises an oscillation circuit configured to generate and provide an oscillating signal. A first biasing circuit is configured to derive a bias current signal in accordance with a control signal and apply the bias current signal to the oscillation circuit to control the amplitude level of the oscillating signal. A reference generating circuit is configured to generate a reference voltage signal and comprises a second biasing circuit configured to derive a reference bias current signal in accordance with the control signal. A comparison circuit is configured to determine an error signal by comparing a voltage signal at an output of the first biasing circuit with the reference voltage signal observed at an output of the second biasing circuit. A controller is configured to determine the control signal related to the error signal and provide the control signal to the first biasing circuit and the second biasing circuit.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract: The present disclosure relates to a method for reducing second order intermodulation distortion in a harmonic rejection mixer arranged for down-converting a radio frequency signal to an in-phase and a quadrature baseband signal. The method includes adjusting an output current of a first mixer, to reduce the second order intermodulation distortion in the quadrature baseband signal to a first value, and adjusting an output current of a second mixer, to reduce the second order intermodulation distortion in the in-phase baseband signal to a second value.

Abstract: A system for compressed sensing comprising: a compressive sampling module configured for providing a CS-sampled signal and a signal reconstruction module configured for receiving and allocating a first plurality of measurement windows comprising a number of samples from the CS-sampled signal, calculating a corresponding first plurality of reconstruction windows based on the first plurality of measurement windows and calculating a first version of a reconstructed signal based on the first plurality of reconstruction windows.

Abstract: A system and a method for monitoring subject's eyes are disclosed. In one embodiment, spectral profiles of a frame substantially around a subject's eye are received from an image capturing device. Further, a state of the subject's eye in the frame is detected using the spectral profiles received from the image capturing device.

Abstract: The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.

Abstract: A communication device is disclosed. The device may be in particular a radio transmitter and a receiver that can operate with low power consumption and with improved interference rejection, therefore particularly suitable for use in low-power communication systems, such as wireless sensor networks and wireless body area networks. In one aspect, multiple frequency tones (carriers) are used to carry information from the transmitter, such that a RF signal having multiple radio frequency components is produced and transmitted. In the receiver, an envelope detector is still the RF down-converter. After down-converting intermodulation components are extracted containing amplitude, phase and frequency information of the multiple radio frequency components. This allows the desired signal (the baseband information) to be distinguished from the carriers and unwanted interference.

Abstract: A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part.

Abstract: Described herein is a pixel readout circuit which provides readout at two sensitivity levels depending on the amount of electrons generated by a pixel photodiode in the circuit. A floating diffusion capacitor operates to store charge up to a saturation value determined by its capacitance and an overflow capacitor is provided in an overflow region for storing charge above the saturation value of the floating diffusion capacitor. Readout at a high sensitivity level is provided when the floating diffusion capacitor is not saturated and readout at a lower sensitivity level is provided when there is saturation and subsequent overflow to the overflow region. Connection of the floating diffusion capacitor to the overflow capacitor shares the charge over the combined capacitance of the two capacitors and provides readout at a lower sensitivity without loss of charge.

Abstract: The present disclosure relates to a method of integrating a interposer device with a textile layer, wherein the interposer device is a stretchable interposer device comprising a stretchable electrically conductive structure with at least one contact pad for establishing at least one electrically conductive path towards the textile layer. The interposer device is arranged to be mechanically attached to a textile layer comprising a plurality of yarns, at least one of which is an electrically conductive yarn. An electrical connection is established between the at least one conductive yarn of the textile layer and the at least one contact pad, which electrical connection is established after the interposer device has been mechanically attached to the textile layer.

Abstract: An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.