Abstract: A spectral camera having an objective lens, an array of lenses for producing optical copies of segments of the image, an array of filters for the different optical channels and having an interleaved spatial pattern, and a sensor array to detect the copies of the image segments is disclosed. Further, detected segment copies of spatially adjacent optical channels have different passbands and represent overlapping segments of the image, and detected segment copies of the same passband on spatially non-adjacent optical channels represent adjacent segments of the image which fit together. Having segments of the image copied can help enable better optical quality for a given cost. Having an interleaved pattern of the filter bands with overlapping segments enables each point of the image to be sensed at different bands to obtain the spectral output for many bands simultaneously to provide better temporal resolution.

Abstract: A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of a baseband signal is disclosed. The circuit comprises a first and a second baseband section arranged for generating a first and a second version of a baseband signal, the second version being phase shifted with respect to the first version. The circuit further comprises three signal paths comprising mixers for multiplication of the first and second version of the baseband signal with a local oscillator signal, so that three upconverted signals with rotated phase with respect to each other are obtained, and arranged for applying a scaling with a scaling factor corresponding to the rotated phases. The circuit further comprises a combination unit arranged for combining the three upconverted signals.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A digital CMOS circuit comprising at least one pull-up circuit arranged, when in an on-state, to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit further comprises at least one pull-down circuit arranged, when in an on-state, to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit further comprises at least one performance matching transistor serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor in such a way so as to compensate for the performance mismatch between the at least one first and second type transistors.

Abstract: A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract: The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described.

Abstract: A imaging system and method is disclosed. In one aspect, the system includes a first edge-detecting module configured to detect edge coordinates in the first image, a first disparity-estimating module configured to obtain a first estimated disparity map of the first image relative to the second image, and a first edge-refining module configured to refine edge coordinates in the first estimated disparity map using the edge coordinates in the first image to obtain a first refined disparity map. The imaging system and method improve the quality of a disparity map and control the complexity of stereo-matching.

Abstract: A system for heart rate detection includes a random sampling module configured to provide nonuniform random samples below a Nyquist rate of a biosignal that contains heart rate information; and a heart rate detection module configured to receive a plurality of the nonuniform random samples during a predetermined time window, calculate a power spectral density based on a Lomb-Scargle periodogram of the window samples and calculate a heart rate value based on a frequency corresponding to a highest power peak of the calculated power spectral density. The disclosure also relates to a corresponding method for heart rate detection and a non-transitory computer readable medium.

Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

Abstract: A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole exposing a metal surface and, optionally, an oxide surface. In one example, the method may include applying a self-assembled monolayer selectively on the exposed metal surface and/or on the oxide surface. The method may also include growing a metal on the self-assembled monolayer and on the exposed metal surface if no self-assembled monolayer is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal structure. The method may further include replacing the first sacrificial layer by a replacement dielectric layer having a dielectric constant of at most 3.9.

Abstract: The disclosed technology generally relates to semiconductor-on-insulator (SOI) devices and more particularly to SOI devices having a channel region comprising a Group III-V or a Group IV semiconductor material, and also relates to methods of fabricating the same. In one aspect, a method comprises providing a pre-patterned donor wafer, providing a handling wafer and bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer. Providing a pre-patterned donor wafer comprises providing a donor substrate comprising a first semiconductor material, forming shallow trench isolation (STI) regions in the donor substrate, and forming fins in the donor substrate in between the STI regions, where each fin comprises a Group III-V or Group IV semiconductor material that is different from the first semiconducting material and laterally extends in a direction parallel to a major surface of the donor substrate and between the STI regions.

Abstract: An optical lens device has an actively controllable focal length. This device comprises an element with lensing effect comprising a plurality of regions. Each such region has a corresponding refractive power for providing a corresponding focal length distinct from the focal length of at least one other region of this plurality of regions. The device further comprises at least one non-centric addressable optical element integrated in or provided on the element with lensing effect. This at least one addressable optical element is adapted for changing the transmittance of at least one of the plurality of regions in response to a control signal. The device also comprises a control means for generating the control signal.

Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.

Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract: A method is provided for forming an unsupported MoS2 layer in an aqueous medium, the method comprising the steps of: providing an assembly of a Mo oxide layer on a Si substrate; annealing said assembly in presence of H2S at a temperature sufficient for forming a MoS2 layer; and contacting the annealed assembly with an aqueous medium. This unsupported MoS2 layer can then be transferred by dip-coating to another substrate such as a dielectric substrate.

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract: The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack.

Abstract: An active pixel sensor imaging system is disclosed. In one aspect, the system includes a plurality of active pixel sensor circuits arranged into an array of rows and columns. Each active pixel sensor is connected to a supply line and a column line, and operable to generate a voltage output through the column line corresponding to a detected light intensity. The system includes a current sensing circuit, located external to the plurality of active pixel sensor circuits and connected to the supply line. The current sensing circuit is implemented as a current mirror for sensing a current through an active pixel sensor circuit readout transistor. The system includes a feedback circuit, located external to the plurality of active pixel sensor circuits and connected to the column line, to a current generator and to the current sensing circuit. The feedback circuit is implemented as a classAB current mirror configured for controlled quiescent current.

Abstract: A spectroscopic apparatus and method for analyzing a biological material are provided. The spectroscopic apparatus may analyze a biological material which has an internal non-uniform tissue depending on a position thereof. The apparatus may include at least one detector configured to obtain respective detection spectrums corresponding to a plurality of measurement regions that are at mutually different positions of the biological material, and an information processor to determine whether the measurement regions are normal by mutually comparing the detection spectrums, or converting contribution degrees of data for a specific component of the biological material by differentiating the detection spectrums.