Abstract: An energy harvesting circuit is based on a switch mode inductive DC-DC converter circuit. The inductor current is sensed and a duration of an on-time is controlled in dependence on the sensed inductor current. A duration of an overall switching period of the converter circuit is controlled in dependence on an on-time set by a first timing control circuit and input and output voltages. This converter circuit enables independent control of the on-time and a full period of a converter cycle. Very rapid switching can be avoided which can give rise to very high energy consumption. The full cycle period can be set to achieve a desired constant value of an input resistance of the DC-DC converter, and thereby maximize power transfer.

Abstract: A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.

Abstract: Methods and devices for holographic imaging are disclosed. In some embodiments, a holographic imaging device is disclosed that includes at least one radiation source, a reflective surface, and an image sensor. The at least one radiation source may be configured to emit a radiation wave towards the reflective surface and an object positioned on or near the reflective surface, where the radiation wave is reflected by the reflective surface to produce a reference wave and is reflected directly toward the image sensor by the object to produce an object wave directed at the image sensor. Further, the image sensor may be configured to determine an interference pattern between the reference wave and the object wave. A holographic image representing the object may be reconstructed based on the interference pattern.

Abstract: An instrumentation amplifier includes a first amplifier having one input connected to a first input of the instrumentation amplifier, a second amplifier having one input connected to a second input of the instrumentation amplifier, and a feedback network. The feedback network including an active filter having a first low pass filter characteristic with a first cut-off frequency in respect of differential mode signals at the first and second inputs of the instrumentation amplifier, and a second low pass filter characteristic with a second cut-off frequency in respect of common mode signals at the first and second inputs of the instrumentation amplifier. The disclosure also relates to a device for acquiring biopotential signals and a signal amplification method.

Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.

Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

Abstract: A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly spin transfer torque magnetic random access memory (STTMRAM) elements having perpendicular magnetic anisotropy (PMA). In one aspect, a magnetic element comprises a metal underlayer and a seed layer on the underlayer, the seed layer comprising alternating layers of a first metal and a second metal. The alternating layers of a first metal and a second metal are repeated n times with, 2<=n<=20.

Abstract: The disclosed technology relates generally to electromechanical devices, and relates more specifically to a nanoelectromechanical switch device and a method for manufacturing the same. In one aspect, an electromechanical device includes a first electrode stack and a second electrode stack, both electrode stacks extending in a vertical direction relative to a substrate surface and being spaced apart by a gap.

Abstract: A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.

Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.

Abstract: A method for lithography is disclosed. The method includes obtaining a self-organizing block-copolymer layer on a neutral layer overlying a substrate, the self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, the self-organizing block-copolymer layer furthermore comprising a copolymer pattern structure formed by micro-phase separation of the at least two polymer components. Further, the method includes etching selectively a first polymer component of the self-organizing block-copolymer layer, thereby remaining a second polymer component. Still further, the method includes applying a plasma etching to the neutral layer using the second polymer component as a mask, wherein the plasma etching comprises an inert gas and H2.

Abstract: A plasmonic structure comprises a substrate and an electro conductor provided in or on the substrate. The electro conductor comprises a first part configured to provide a first series of plasmon resonance modes (for incident radiation of a first wavelength) and a second part configured to provide a second series of plasmon resonance modes (for incident radiation of a second wavelength). The first and second parts are functionally connected in a linkage region, wherein the electro conductor is shaped such as to form a capacitive gap. The electro conductor is further configured to direct radiation incident on the plasmonic structure of the first wavelength predominantly toward a first direction and to direct radiation incident on the plasmonic structure of the second wavelength predominantly toward a second direction, in which the first direction and the second direction are separated by an angle of at least 60°.

Abstract: A holographic imaging device for imaging an object under study includes a partially reflective surface having a contact side for contacting the object under study and an imaging side for partially reflecting a radiation wave. The device also includes at least one radiation source for projecting the radiation wave onto the imaging side of the partially reflective surface and an image sensor arranged to receive the radiation wave when reflected by the partially reflective surface. The image sensor is adapted for determining an interference pattern between the radiation wave reflected by the imaging side of the partially reflective surface and the radiation wave reflected by the object under study when contacting the contact side of the partially reflective surface.

Abstract: Disclosed are microelectromechanical system (MEMS) devices and methods of using the same. In some embodiments, a MEMS device comprises a micro-oven comprising a MEMS oscillator configured to generate a reference signal. The device further comprises a control unit comprising at least one input node configured to receive a parameter set, where the parameter set comprises at least a first parameter indicative of a sensed ambient temperature, and where the control system is configured to (i) based on the parameter set, select from a plurality of pre-characterized operation temperatures an operation temperature for the MEMS oscillator, and (ii) generate a temperature-setting signal indicating the selected operation temperature. The device still further comprises a temperature control system communicatively coupled to the control unit and configured to (i) receive the temperature-setting signal and (ii) maintain the MEMS oscillator at the selected operation temperature.

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.