Abstract: A cluster of non-collapsed nanowires, a template to produce the same, methods to obtain the template and to obtain the cluster by using the template, and devices comprising the cluster are described. The cluster and the template both have an interconnected region and an interconnection-free region.

Abstract: A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract: An optical device is provided for coupling an external optical signal into a plurality of on-chip photonic sub-circuits provided on a substrate. The optical device comprises: a planar waveguide layer on the substrate; a diverging grating coupler configured to couple the external optical signal to the planar waveguide layer and to thereby create an on-chip diverging optical beam in the planar waveguide layer; and a plurality of channel waveguides formed in the waveguide layer. Each channel waveguide of the plurality of channel waveguides comprises a waveguide transition structure having a waveguide aperture oriented towards the diverging grating coupler. For each channel waveguide of the plurality of channel waveguides the position and the width of the corresponding waveguide aperture and the angle and the shape of the waveguide transition structure are individually selected to capture a predetermined portion of the on-chip diverging optical beam.

Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: A stretchable electronic device is disclosed. In one aspect, the device has a stretchable interconnection electrically connecting two electronic components. The stretchable interconnection includes an electrically conductive channel having a predetermined first geometry by which the channel is stretchable up to a given elastic limit and a first flexible supporting layer provided for supporting the electrically conductive channel and having a predetermined second geometry by which the first supporting layer is stretchable. The predetermined second geometry has a predetermined deviation from the predetermined first geometry chosen for restricting stretchability of the electrically conductive channel below its elastic limit.

Abstract: Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behavior of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N?1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations.

Abstract: A photovoltaic device is disclosed. In one aspect, the device is formed in a semiconductor substrate. It has a radiation receiving front surface and a rear surface. The device may have a first region of one conductivity type, a second region with the opposite conductivity type adjacent to the front surface, and an antireflection layer. The rear surface is covered by a dielectric layer covering also an inside surface of the via. The front surface has current collecting conductive contacts. The rear surface has conductive contacts extending through the dielectric. A conductive path is in the via for photogenerated current from the front surface. By having the dielectric all over, no aligning and masking is needed. The same dielectric serves to insulate, provide thermal protection, and helps in surface and bulk passivation. It also avoids the need for a junction region near the via, hence reducing unwanted recombination currents.

Abstract: Described is an (organic) light-emitting diode ((O)LED) wherein the light-emitting layer comprises a blend of an electroluminescent semiconducting material with a ferro-electric material. Either of the electrodes forms a modulatable injection barrier with the ferro-electric material, the modulation requiring a voltage Vm serving to polarize or repolarize the ferro-electric material. With Vm being larger than the voltage Ve required for light emission, the (O)LED can be turned “on” or “off” by applying a pulse voltage to (re)polarize the ferro-electric material.

Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

Abstract: The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.

Abstract: An imaging system and method are disclosed. In one aspect, the system includes an edge-detecting module detecting edge coordinates in a first image; first and second disparity-estimating modules respectively configured to obtain a first and second estimated disparity map, a cross-checking module configured to cross check the first estimated disparity map using the second estimated disparity map to identify occlusion pixels in the first estimated disparity map, an occlusion-refining module configured to refine the occlusion pixels by identifying at least a pixel under refinement on the first estimated disparity map as occluded based on the number of occlusion pixels in a refining base region, and a hole-filling module configured to fill the refined set of occlusion pixels. The imaging system improves the quality of a disparity map and controls the complexity of stereo-matching.

Abstract: A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.

Abstract: A method an system is disclosed for characterizing DNA and/or RNA duplexes. The biosensing device comprises a heating element using a power and being suitable for providing thermal denaturation of target DNA and/or RNA bioparticles, a sample holder adapted for receiving a biocompatible substrate having a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes can be attached, the sample holder further being adapted for exposing the biocompatible substrate at one side to the heating element, a first temperature sensing element for sensing a temperature at the side where the biocompatible substrate can be exposed to the heating element and a second temperature sensing element for sensing a temperature at the side opposite thereto with respect to the biocompatible substrate.

Abstract: Disclosed are methods for fabricating pyrolysed carbon nanostructures. An example method includes providing a substrate, depositing a polymeric material, subjecting the polymeric material to a plasma etching process to form polymeric nanostructures, and pyrolysing the polymeric nanostructures to form carbon nanostructures. The polymeric material comprises either compounds with different plasma etch rates or compounds that can mask a plasma etching process. The plasma etching process may be an oxygen plasma etching process.

Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.

Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.

Abstract: Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror elements arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt angle range, and each micro-mirror element in the second section has a second tilt angle range, with the first tilt angle range being less than the second tilt angle range.