Abstract: A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A method for digital driving of an active matrix display with a predetermined frame rate is described. The display contains a plurality of pixels organized in a plurality of rows and a plurality of columns. The method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code. The method also includes dividing the image frame into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row and upon a second selection a second digital code is written to the selected row. There is a predetermined time delay between the second selection and the first selection. Digital driving circuitry is also described.

Abstract: Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.

Abstract: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

Abstract: An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.

Abstract: A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an array of mirrors, an array of filters for passing a different passband of the optical spectrum for different ones of the optical channels arranged so as to project multiple of the optical channels onto different parts of the same focal plane, and a sensor array at the focal plane to detect the filtered image copies simultaneously. By using mirrors, there may be less optical degradation and the trade off of cost with optical quality can be better. By projecting the optical channels onto different parts of the same focal plane a single sensor or coplanar multiple sensors can to be used to detect the different optical channels simultaneously which promotes simpler alignment and manufacturing.

Abstract: The present invention relates to an integrated photonic device comprising a photonic substrate, and an integrated waveguide provided in or on this substrate. The waveguide is adapted for conducting radiation of a predetermined wavelength. The device further comprises a sub-wavelength grating optically connected to the waveguide, which provides a first periodic variation of the refractive index in at least one first spatial direction. The device also comprises a diffracting grating arranged over the sub-wavelength grating for coupling radiation of the predetermined wavelength in and/or out of the integrated waveguide via the sub-wavelength grating. The diffracting grating provides a second periodic variation of the refractive index in at least one second spatial direction. The first periodic variation has a first pitch that is less than half of the predetermined wavelength, while the second periodic variation has a second pitch that is at least half of the predetermined wavelength.

Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.

Abstract: A resonator structure is disclosed. In some embodiments, the resonator structure may include a metal-insulator-metal waveguide comprising a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, wherein the insulating layer comprises a resonating cavity. The resonator structure may further include a mirror formed in the resonating cavity, wherein the mirror comprises at least one nanoscale metallic reflector positioned at least partly in the insulating layer.

Abstract: A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, a mosaic of filters for passing different bands of the optical spectrum, and a sensor array arranged to detect pixels of the image at the different bands passed by the filters, wherein for each of the pixels, the sensor array has a cluster of sensor elements for detecting the different bands, and the mosaic has a corresponding cluster of filters of different bands, integrated on the sensor element so that the image can be detected simultaneously at the different bands. Further, the filters are first order Fabry-Perot filters, which can give any desired passband to give high spectral definition. Cross talk can be reduced since there is no longer a parasitic cavity.

Abstract: Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate. In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and amplified signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream. Such a multi-level to binary converter is capable of performing at data rates of 50 to 80 Gb/s and above, and can easily be integrated within a chip for high-speed electrical backplane communication, optical backplanes or optical fibre links.

Abstract: A method for evaluating the quality of a directed self-assembling method used for generating directed self-assembling patterns. The method for evaluating comprises obtaining at least one set of parameter values for a parameterized set of processing steps and material properties characterizing the directed self-assembling method, thus characterizing a specific directed self-assembling method used for generating a directed self-assembled pattern. The method furthermore comprises obtaining a scattered radiation pattern on the directed self-assembled pattern obtained using the directed self-assembling method characterized by the set of parameter values, thus obtaining scattered radiation pattern results for the directed self-assembled pattern. The method furthermore comprises determining based on the scattered radiation pattern results a qualification score and correlating the qualification score with the set of parameter values.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: An integrated fluorescence detector for detecting fluorescent particles is described. An example integrated fluorescence detector comprises a substrate, the substrate comprising an integrated detection element for detecting fluorescence radiation from fluorescent particles upon excitation of the particles with incident excitation radiation. The integrated fluorescence detector also comprises a sensing layer adapted for accommodating fluorescent particles to be sensed. The integrated fluorescence detector further comprises a photonics crystal layer arranged in between the sensing layer and the substrate, the photonics crystal layer comprising an absorption material designed such that the photonics crystal layer is configured for diffracting incident excitation radiation into a lateral direction in which the photonics crystal layer extends for incident excitation radiation having a wavelength within at least 10 nm of the predetermined excitation wavelength.

Abstract: A sensing device for sensing a substance includes a photonics integrated circuit having a resonator element that supports two different radiation modes, e.g. radiation modes of different polarisation, at a predetermined resonance wavelength. The resonator element is configured to convert a phase change or amplitude change experienced by the two different radiation modes upon formation of a layer of receptor molecules onto a sensing surface of the device into a resonance wavelength shift for the two different radiation modes. The sensing device also includes a detection unit arranged to detect the resonance wavelength shift for the two different radiation modes. The detection unit includes a processor that is configured to derive from the detected resonance wavelength shifts for the two different radiation modes, a layer thickness and refractive index of the layer of receptor molecules.

Abstract: An apparatus and method for low-power sensing, for example, sensing of chemical or biochemical analytes in a gas or liquid phase are disclosed. One aspect relates to the use of a thin continuous film without grain boundaries as a sensing layer in devices for sensing a predetermined analyte and to low power devices having such sensing layer. The sensing layer has a surface exposed to the analyte. The electrical impedance of the sensing layer changes upon adsorption of the predetermined analyte on the exposed surface of the sensing layer. The sensing layer may have a thickness in the range between about 1 nm and 100 nm, such as between about 1 nm and 30 nm. The sensing layer may be an amorphous layer.

Abstract: A photonic integrated device comprises a waveguide embedded in a photonic substrate. The waveguide has a waveguide radiation exit surface and the waveguide is optically connected to a two dimensional grating. The photonic integrated device also comprises a two dimensional grating having a plurality of curved elongate scattering elements. The two dimensional grating is adapted for diffracting radiation received from the waveguide toward a direction out of the photonic substrate and the curved elongate scattering elements are oriented with respect to the waveguide such that, for points of the scattering elements which can be irradiated by radiations stemming from the waveguide, normal lines to at least the curved elongate scattering element closest to the waveguide radiation exit surface do not substantially intersect with the waveguide radiation exit surface of the waveguide.

Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.