Abstract: A method for module-level processing of photovoltaic cells is provided. The method includes: bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, thereby leaving part of the adhesive layer uncovered; after bonding, exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a plasma; and removing a surface portion of the at least one crystalline photovoltaic substrate. The method may further include performing an annealing step of the adhesive before bonding the at least one photovoltaic substrate to the carrier, and performing an outgassing step of the adhesive after bonding the at least one photovoltaic substrate to the carrier. The method may further include module-level rear side processing of the at least one crystalline silicon photovoltaic substrate to make a photovoltaic module.

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n?1) different reference values, and having N sets of (n?1) output terminals for outputting N sets of (n?1) output signals indicating whether the value of the multi-level signal is below or above the (n?1) reference values. The circuitry also includes N sets of (n?1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n?1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract: A method is provided for activating an exposed surface of a porous dielectric layer, the method comprising the steps of: filling with a first liquid at least the pores present in a part of the porous dielectric layer, the part comprising the exposed surface, removing the first liquid selectively from the surface, activating the exposed surface, and removing the first liquid from the bulk part of the porous dielectric layer.

Abstract: A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames.

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and ?110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30 s.

Abstract: An apparatus (100) for performing atomic force microscopy is disclosed. The apparatus comprises an AFM measurement unit (102) configured to operate in a first controlled atmosphere (300) and a pretreatment unit (101) configured to operate in a second controlled atmosphere (400), the second controlled atmosphere being different from the first controlled atmosphere. The pretreatment unit is connected to the AFM measurement unit. In one embodiment, the second controlled atmosphere is a vacuum atmosphere, whereas the first controlled atmosphere includes at least an inert gas.

Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.

Abstract: Disclosed are methods and systems for determining a topography of a lithographic optical element and/or a holder of a lithographic optical element. In one embodiment, the method includes directing electromagnetic radiation towards a lithographic optical element, where the electromagnetic radiation comprises electromagnetic radiation in a first predetermined wavelength range and electromagnetic radiation in a second predetermined wavelength range. The method further includes using the lithographic optical element to adsorb the electromagnetic radiation in the first predetermined wavelength range, and to reflect at least a portion of the electromagnetic radiation in the second predetermined wavelength range towards a substrate comprising a photosensitive layer, thereby exposing the photosensitive layer to form an exposed photosensitive layer.

Abstract: A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.

Abstract: The present disclosure relates to a front-end system for a radio device. In one example, a front-end system comprises a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator, and characterized in that, the converter further comprises a quantizer arranged for quantizing the baseband signal into a digital signal. Further, the signal generator may be configured for generating, based on the digital signal, the local oscillator signal such that it is synchronized with the radio frequency signal.

Abstract: The present disclosure relates to a modulation circuit and a method for suppressing energy content of spectral side lobes caused by high-frequency content present in a baseband signal, with the energy content of the spectral side lobes being outside an intended operational bandwidth in a modulated radio-frequency signal. An example circuit is configured to: receive a digital baseband signal, feed the digital baseband signal to a first and a second signal path, with the first signal path comprising a first mixer and the second signal path comprising a delay circuit and a second mixer. The first mixer and the second mixer may receive a same local oscillator signal, and may respectively provide a first radio-frequency signal and a second radio-frequency signal that are delayed with respect to each other. The example circuit is further configured to generate an output radio-frequency signal by combining the first and second radio-frequency signals.

Abstract: A method for manufacturing a SERS sensing device (100), the method comprising: providing a silicon substrate (101), creating a silane layer (102) on a surface of the silicon substrate (101), and creating a plurality of plasmonic nanostructures (103) on the silane layer (102), characterized in that: creating a plurality of plasmonic nanostructures (103) on the silane layer (102) comprises completely covering the silane layer (102) with a metallic plasmonic layer (104). Further a SERS sensing device is presented which is implantable.

Abstract: A method an system is disclosed for the detection and/or allocation of at least one point mutation in target DNA and/or RNA duplexes. The method comprises obtaining a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes are attached, contacting said functionalized surface to an electrolytic solution having a neutral pH in a flow cell and measuring a first impedance value within said electrolytic solution, and then adding a chemical to the electrolytic solution which is able to achieve denaturation of the target DNA and/or RNA. The method further comprises measuring a second impedance value within the flow cell after completion of the denaturation of the DNA and/or RNA target, and then obtaining a value representative for the impact of the chemical on the impedance of the electrolytic solution.

Abstract: A biopotential signal acquisition system comprising an analogue readout unit configured to receive an analogue biopotential signal and to extract an analogue measured biopotential signal and an analogue reference signal, and an ADC unit configured to provide a digital version of the analogue measured biopotential signal and the analogue reference signal. The system also includes a first digital filter unit comprising a cascaded integrator-comb filter configured to provide a first digital filtered version of the digital measured biopotential signal and the reference signal, and a second digital filter unit configured to calculate a digital motion artifact estimate based on the first digital filtered version signals.

Abstract: The present disclosure relates to a timing synchronization circuit for a digital receiver structure that includes a timing error detection module comprising a phase difference calculation unit arranged for calculating a phase difference between incoming samples of a digital data stream, and a timing error estimator arranged for determining a timing error estimate based on the calculated phase difference, and for generating, based on the determined timing error estimate, a signal indicative of timing error detection. The circuit also includes a timing error control module arranged for receiving the signal indicative of timing error detection, for evaluating the number of received signals indicative of timing error detection and for outputting, after comparison with a threshold value, a sampling adjustment command for adjusting the sampling instants applied for obtaining the digital data stream.

Abstract: A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.