Abstract: Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.

Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.

Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.

Abstract: A method and/or system may be configured to receive an input/output (I/O) request from an initiator system, add priority information to a multiple path referral for each port on which data can be accessed, selectively omit ports on which data may be accessed, transmit the multiple path referral from the target to the initiator, and/or choose a path on the initiator with the highest performance.

Abstract: An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.

Abstract: Embodiments of the invention include a dictionary based data compression method, apparatus and system that is not based on either the LZ77 compression algorithm or the LZ78 compression algorithm, but includes many features of the LZW compression algorithm. The data compression method includes creating a mapping table of the messages in the alphabet of messages to a corresponding plurality of codewords, maintaining a dictionary including a mapping table of a first codeword and a second codeword to a new codeword, reading an input ensemble including a plurality of messages, converting the messages to an input codeword using the mapping table, and outputting the converted codewords as an output ensemble of compressed data. Unlike conventional data compression methods, the dictionary is generated from the output ensemble only, and is not based on any input messages. Therefore, the dictionary more quickly builds to define longer sequences of messages compared to conventional data compression methods.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: A method for testing a provider in a common information model. The method generally includes the steps of (A) generating a test case class of the common information model, the test case class residing in a class hierarchy of an object-oriented model, (B) generating a client test case class of the common information model below the test case class in the class hierarchy, the client test case class defining control of at least one logical configuration for the provider and (C) generating an instance tester class of the common information model below the client test case class in the class hierarchy, the instance tester class defining at least one verification module for testing the provider.

Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SATA and/or SAS standards and causing communication between one or more hosts and a SATA device. A multi-port bridge device is in communication with the one or more hosts through at least one link, the bridge device includes a power control block operative to control power to a SATA device through a power connection, wherein the power control block causes power to be provided to the SATA device even when the at least one link is operational.

Abstract: An apparatus may include drive chassis, at least one horizontal drive drawer extending from a first side of the drive chassis to a second side of the drive chassis and/or at Least one computer drive disposed on the horizontal drive drawer. Additionally, a computer server system and a method for providing the apparatus are disclosed.

Abstract: In one embodiment, a tape measure having a tape, housing, and an input, has an OLED strip overlaid on top of the tape. The housing contains a programmable controller and a rolled-up portion of the tape. A specified fraction of the length of the linear target is provided to the controller using the input. The tape may be extracted from the housing to generate an exposed portion of the tape corresponding to the total length of a linear target. The controller receives information indicative of the total length of the linear target. The controller controls the OLED strip to show, i.e., light up along the tape, a fractional portion corresponding to the specified fraction of the linear target.

Abstract: An apparatus comprising a transmodulator unit. The transmodulator unit generally comprises (i) a first input configured to receive a baseband video signal, (ii) a second input configured to receive a first encoded data signal and (iii) an output configured to present a second encoded data signal. The second encoded data signal is generated in response to the first encoded data signal and the baseband video signal. The first encoded data signal comprises an advanced data signal. The second encoded data signal comprises a legacy data signal.

Abstract: Embodiments include methods and systems for processing XML documents. One embodiment is a system that includes a method of efficiently processing XML documents received concurrently from a plurality of network connections in the form of streams of data. Other embodiments include systems configured to perform such processing of streamed XML documents. Other embodiments include systems and methods of efficiently performing document processing using digests for identifying XML document structure.

Abstract: A method and apparatus for processing a video block extracted from an encoded bitstream. The method generally includes the steps of (A) generating a normal block by inverse transforming the video block, the normal block having a normal resolution, (B) generating an alternate block from the video block, the alternate block comprising image detail (i) present after the inverse transforming and (ii) absent from the normal block and (C) generating an output block based on the normal block and the alternate block, the output block having an output resolution greater than the normal resolution.

Abstract: An electronic device package 100 comprising a lead frame having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.

Abstract: A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.

Abstract: The present invention is directed to a method and system for testing systems involving high speed SERDES cores by exposing an internal nature of signals. The signals are tapped at various external test points. The present invention may take one or more test points in receive and/or transmit paths of high speed SERDES cores, and expose the test points by routing signals to the pins/balls on a chip. Programmable directing (multiplexing) of signals may be utilized to restrict number of output debug ports. Consequently, the number of the pin count required for the chip may be controlled.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.