Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.

Abstract: An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.

Abstract: Methods, apparatus, and systems for generating bit-wise reliability information using a soft output Viterbi algorithm (“SOVA”) in an nT Viterbi decoder implementation devoid of 1T metric information. At each nT clock pulse 1T equivalent metric values are determined from the current nT metric information. 1T equivalent metric information is determined as values that sum to the corresponding nT metric information. Subtraction is then used to determine state metric difference information from the 1T equivalent metric values. The state metric difference information may then be used to estimate log likelihood ratio information for use in the SOVA algorithm to determine bit-wise reliability information.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: Data segments are logically organized in groups in a data repository. Each segment is stored at an index in the data repository. In association with a write request, a hash algorithm is applied to the data segment to generate a group identifier. Each group is identifiable by a corresponding group identifier. The group identifier is applied to a hash tree to determine whether a corresponding group in the data repository exists. Each existing group in the data repository corresponds to a leaf of the hash tree. If no corresponding group exists in the data repository, the data segment is stored in a new group in the data repository. However, if a corresponding group exists, the group is further searched to determine if a data segment matching the data segment to be stored is already stored. The data segment can be stored in accordance with the results of the search.

Abstract: A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power.

Abstract: Power factor correction and driver circuits and stages are described. More particularly, power factor correction circuits are described that utilize an auxiliary inductor winding for power regulation. Driver circuits configured for electrical loads such as series arrangements of light emitting diodes are also described. An exemplary embodiment of a driver circuit can implement a comparator and/or a voltage regulator to allow for improved output current uniformity for high-voltage applications and loads, such as series configurations of LEDs. Embodiments of PFC stages and driver stages can be combined for use as a power supply, and may be configured on a common circuit board. Power factor correction and driver circuits can be combined with one or more lighting elements as a lighting apparatus.

Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

Abstract: An apparatus comprising a circuit configured to translate instruction codes of a first instruction set into sequences of instruction codes of a second instruction set that emulate a functionality of the instruction codes of the first instruction set.

Abstract: Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.

Abstract: Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium, an offset frequency, a read/write head assembly, and a harmonic fly-height change detection circuit. The storage medium includes a periodic data pattern that repeats at a data frequency. The read/write head assembly disposed in relation to the storage medium such that it senses the periodic data pattern and provides a sensed periodic data pattern. The harmonic fly-height change detection circuit samples the sensed periodic data pattern at an aggregate frequency to yield a first set of samples and a second set of samples. The aggregate frequency is the data frequency adjusted by the offset frequency. The harmonic fly-height change detection circuit calculates a first magnitude of the first set of samples and a second magnitude of the second set of samples.

Abstract: A color image sensing apparatus and a method of processing an infrared-ray signal are provided. The image sensing apparatus includes: a color filter array including a plurality of color filter units, each color filter unit including a red-pass filter, a preen-pass filter, and a blue-pass filter, and at least one of the red-, green- and blue-pass filters passing infrared-rays; an image sensor for providing an image signal corresponding to light passing through the color filter array, the image signal including a red light signal, a green light signal, a blue light signal, and an infrared-ray signal; and an image signal processor for correcting and processing at least one of the red light signal, the green light signal and the blue light signal in response to the infrared-ray signal.

Abstract: Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

Abstract: A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die.

Abstract: An optical-disc writer writes extrinsic data to an optical disc. Extrinsic data can be written as (i) embedded marks (e.g., pits and lands) located outside the conventional readable area of a disc and/or (ii) alternative marks, such as surface marks located on a surface of the disc. In an optical-disc player having a disc-reading subsystem and a read controller, the disc-reading subsystem reads and relays the extrinsic data to the read controller, which controls the operations of the player based on the extrinsic data. For example, the writer prints extrinsic data, e.g., a barcode, on the surface of a software installation disc. The disc is inserted in the player and installation is commenced. The read controller instructs the disc-reading subsystem to read the extrinsic information. If the read controller determines that the extrinsic data was successfully read, then installation proceeds; otherwise, installation is halted.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.

Abstract: A method and system for detecting and isolating memory leak in RAID controllers utilizing sequence numbers. The system monitors whether the count of un-freed memory blocks for a sequence number (SN) zone (after a start-of-day SOD operation, but smaller than the current sequence number zone) is not eventually decremented to zero. The memory leak can be detected when un-freed memory blocks exist and follow a similar pattern with respect to all other adjacent SN zones. The detected memory leak can be isolated utilizing shell commands, task information, caller information, sequence number, memory allocation size and a pointer to the next allocated memory block.