Abstract: Methods and apparatus for configurably limiting performance of an I/O controller device in processing of I/O requests. A performance monitor and control module in the I/O controller device monitors performance of the I/O request processing module and limits its processing to assure that maximum performance threshold values are not exceeded. In one embodiment, the performance monitoring may average performance over one or more periods of time and may provide a moving average window to determine the performance of the I/O controller device. The measured performance may determine a variety of performance measures each of which may be compared against one or more corresponding maximum performance threshold values. Requests that cannot be processed during a present period of time are delayed until a subsequent period of time to thereby limit performance of the I/O controller device.

Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using end device grouping. A SAS end device grouping management application is configured to group SAS end devices, such as SAS initiator devices and SAS target devices, into any number of zones or zone configurations. The end device grouping application uses these defined zones to create a minimal number of zone groups, e.g., by creating one zone group per defined zone and populating the zone group with the ZPSDS entry point phys of the end devices in the zone from which the zone group is based, and to configure the respective permissions of the created zone groups. The end device grouping application then compares all existing zone groups for common phys and removes them to a new zone group. The zone groups are compared and processed in this manner until no zone groups have common phys.

Abstract: An AC/DC power supply, a method of delivering DC power at multiple voltages and a computer data storage system. In one embodiment the AC/DC power supply includes: (1) a transformer having a primary winding couplable to an AC power source and a secondary winding inductively couplable to the primary winding and (2) multiple DC voltage rails coupled to the secondary winding at designated locations and configured to deliver power to loads coupled thereto, each of the DC voltage rails configured to dynamically transfer therebetween an available portion of the power in response to changes in the loads.

Abstract: A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).

Abstract: An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species.

Abstract: A light fixture useful in the lighting of parking garages, including a base, a reflector element and at least one light-emitting lamp. The reflector element includes a reflector portion that extends vertical from the base to a distal edge that extends beyond the lamp. The extending reflector portions include a plurality of planer panels positioned in a plane at an angle that faces toward the lamp. A portion of the emitted light is reflected by the extending reflector portion in the opposed horizontal direction away from the fixture at a reflected angle from nadir that is greater than the emitted angle. The light fixture provides a uniform lighting pattern that allows for using fewer of the light fixtures, by projecting or reflecting emitted light horizontally at very high angles from nadir, and delivering more light to areas laterally remote from the fixture, and potentially using less energy.

Abstract: Apparatus, systems, and methods for coupling Fiber Channel (FC) storage devices and serial attached SCSI (SAS) storage device to a computer system through a single host bus adapter (HBA). The HBA includes a SAS storage controller four coupling to one or more SAS storage devices and an FC interface for coupling to one or more FC storage devices. The HBA also includes translation logic to translate information exchanged between the SAS storage controller and the FC storage device(s). Translation may include translation of addressing information between FC protocols and formats used by the SAS storage controller, may include use of a buffer to enable exchanges at different data rates, and may include use of a buffer to aggregate an inbound FC multiframe sequence into a single data buffer for use by the SAS storage controller.

Abstract: Methods and systems for metadata management in a storage system are disclosed. First level metadata is associated with a plurality of storage devices in a storage system. Entries in the first level metadata identify storage related attributes of corresponding portions on the plurality of storage devices. Entries in a second level metadata are associated with a corresponding plurality of entries in the first level metadata, where the second level metadata identifies metadata related attributes of the corresponding first level metadata entries. Responsive to receiving a request for a storage related attribute in the first level metadata table, the storage related attribute is derived from the second level metadata table, which reduces the first level metadata processing requirements and increases the performance of the storage system.

Abstract: Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof.

Abstract: A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal.

Abstract: Methods and systems for managing RAID volumes are disclosed. Metadata is associated with storage devices that comprise a RAID volume. The metadata identifies each of a plurality of portions as being either initialized or non-initialized. The number of I/O operations performed by a storage controller coupled with the storage devices is reduced in response to a request for the RAID volume based on the metadata.

Abstract: A set of data is allocated into a plurality of data chunks, wherein the plurality of data chunks is thinly provisioned and erasure coded. A plurality of storage devices is divided into a first and a second set of storage devices, wherein the first set of storage devices is powered up and the second set of storage devices is powered down. The data chunks are distributed on the first set of storage devices to equally load each of the first set of storage devices. A storage device from the second set of storage devices is powered up to reassign the storage device from the second set of storage devices to the first set of storage devices. Data chunks are migrated to a reassigned storage device until the data chunks are evenly distributed on the first set of storage devices and the reassigned storage device.

Abstract: An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.

Abstract: A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.

Abstract: A method for transcoding from an H.264 format to an MPEG-2 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the H.264 format to generate a picture having a plurality of macroblock pairs that used an H.264 macroblock adaptive field/frame coding; (B) determining a mode indicator for each of the macroblock pairs; and (C) coding the macroblock pairs into an output video stream in the MPEG-2 format using one of (i) an MPEG-2 field mode coding and (ii) an MPEG-2 frame mode coding as determined from the mode indicators.

Abstract: Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.

Abstract: A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates.

Abstract: Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.

Abstract: Methods and systems for automatically, dynamically reconfiguring multiplexing functions of a PHY of a SAS device in response to monitored performance of the PHY and/or in response to changes in configuration of devices in the SAS domain. A SAS device such as a SAS initiator or a SAS expander in a SAS domain may monitor performance of PHYs of the device to detect bandwidth utilization and may reconfigure multiplexing functions of a PHY to improve bandwidth utilization of the PHYs of the device. The device may also detect changes in the topology of the SAS domain such as addition of new devices or removal of device and adjust multiplexing functions of its PHYs accordingly to improve performance of communications in the SAS domain.