Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Abstract: A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line, a read address is received on the read address line, data is received on the data in line. The comparator determines as a first condition whether the write address is identical to the read address, and determines as a second condition whether the write enable line is enabled. When both the first condition and the second condition are met, the comparator signals the mux to directly output the data receiving on the data in line on the data out line without writing the data to the bit array. In this manner, the memory circuit checks to determine whether a write-through operation is called for.

Abstract: An apparatus generally comprising an input circuit, a storage circuit and an output circuit is disclosed. The input circuit may be configured to generate a first intermediate signal from a plurality of input video signals. The storage circuit may be configured to (i) organize the first intermediate signal into a plurality of sequences each related to one of the input video signals and (ii) generate a second intermediate signal from the sequences. The output circuit may be configured to generate an output video signal by compressing the second intermediate signal.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract: A method for transcoding from a VC-1 format to an MPEG-2 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the VC-1 format to generate a picture; (B) determining a first mode indicator for the picture; and (C) coding the picture into an output video stream in the MPEG-2 format using one of (i) an MPEG-2 field mode coding and (ii) an MPEG-2 frame mode coding as determined from the first mode indicator.

Abstract: A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.

Abstract: The present disclosure is directed to a method for providing continuous data protection for a virtual volume (VV). The method may comprise conceptually dividing the VV into a plurality of same sized chunks; preserving contents of the VV at a specified time; creating a Point in Time (PiT) instance for the VV at the specified time, comprising: a PiT Temporary Virtual Volume (PTVV) for storing modifications to the VV subsequent to the specified time, wherein data stored in the PTVV is prohibited from been overwritten; a re-allocation table for providing read access to a most recent version of each of the plurality of chunks of the VV; and a Continuous Data Protection (CDP) log for providing read access to a historic version of a chunk stored in the PTVV; and updating the PiT instance when a chunk of the plurality of chunks of the VV is being modified.

Abstract: Data segments are logically organized in clusters in a data repository of a data storage system. Each clusters contains compressed data segments and data common to the compression of the segments, such as a dictionary. In association with a write request, it is determined in which of the clusters would the data segment most efficiently be compressed, and the data segment is stored in that data cluster.

Abstract: An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

Abstract: A method for transitioning a video system is disclosed. The method generally includes a first step for (A) executing in a processing circuit a standby code stored in a nonvolatile memory while the video system is in an off state, the off state defining a low power configuration for the processing circuit and a power off condition for the video system, the standby code being responsive to a plurality of wake up conditions to wake up the video system. In a second step, the method may (B) store an application code in a volatile memory while in the off state, the application code configured to operate the video system while in an on state of the video system. The method generally includes a third step for (C) transitioning from the off state to the on state upon detection of at least one of the wake up conditions. A step for (D) executing in the processing circuit the application code while in the on state to decode video may also exist in the method.

Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.

Abstract: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured.

Abstract: A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to determine frequency of occurrence information for a range of gray levels from luminance data of an input signal. The second circuit may be configured to selectively adjust enhancement for at least one portion of the range of grey levels based upon the frequency of occurrence information.

Abstract: An apparatus including a transmit circuit, a receive circuit, and a control circuit. The control circuit may be configured to present a plurality of transmit data lanes in response to (i) a plurality of transmit data sources and (ii) a plurality of first skew control signals. The receive circuit may be configured to generate a plurality of receive data lanes in response to (i) the plurality of transmit data lanes and (ii) a plurality of second skew control signals. The control circuit may be configured to generate the first skew control signals and the second skew control signals in response to an alignment of the plurality of receive data lanes. The control circuit may adjust a timing of the receive data lanes and the transmit data lanes to achieve arrival of the receive data lanes across a transmission medium within a skew parameter.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) generating a plurality of neighbor scores by searching for the edge along a plurality of neighbor angles proximate a particular angle of the primary angles corresponding to a particular score of the primary scores having a best value and (C) identifying a best score from a group of scores consisting of the particular score and the neighbor scores to generate an interpolated sample at the location.

Abstract: Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In addition, the method includes coupling the plurality of transistors in the transistor layer to the one or more power sources based on a state of the nanotube structure.