Abstract: A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory.

Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

Abstract: Methods and associated structure for rapidly detecting a catastrophic failure of a bus structure within a storage subsystem. Features and aspects hereof associated with SCSI bus storage system configurations coordinate such failure detection with standard monitoring features of the SAF-TE, enclosure monitoring specifications. In particular, standard polling operations of a SAF-TE compliant enclosure may be terminated early so as to preclude queuing additional polling related commands for disk drives or an enclosure of disk drives coupled to a SCSI bus cable or backplane that has experienced a catastrophic failure. Other features and aspects hereof disable all disk drives in a storage system that are coupled to a failed common bus.

Abstract: A method for processing a video signal, comprising the steps of (A) receiving the video signal comprising (i) a first segment having a series of frames each having a first region and a second region defining a first signature and (ii) a second segment having a series of frames each having a first region and a second region defining a second signature, (B) modifying each of the frames of the first segment from the first signature to a third signature and (C) modifying each of the frames of the second segment from the second signature to a fourth signature.

Abstract: A method of improving a serial IO operation, where the serial IO operation includes at least one of a read operation of a data block and a write operation of a data block, and the serial IO operation is directed to a logical disk of a computerized data storage system. Only one stripe of data is read from the logical disk into a cache, and it is determined whether the data block for the IO operation is included within the cache. When the data block for the IO operation is included within the cache, then for a read operation, the IO operation is serviced from the cache. For a write operation, the cache is updated with the data block to be written, and only an updated parity block is written to the logical disk. When the data block for the IO operation is not included within the cache, then for a read operation, only one new stripe of data that includes the data block is read from the logical disk into the cache, and the IO operation is serviced from the cache.

Abstract: An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion of the atoms, (iii) designate a first atom within the strip, (iv) locate one or more second atoms to be paired with the first atom, (v) determine whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (vi) read the legitimate pair from the first memory portion and the second memory portion.

Abstract: A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Abstract: A method for displaying button data streams, comprising the steps of (A) reading two or more input button data streams from a disc, (B) multiplexing the two or more input button data streams to produce a multiplexed button data stream, (C) decoding the multiplexed button data stream into uncompressed button data information, and (D) displaying the uncompressed button data information in a video signal.

Abstract: A DAS system that implements RAID technology is provided in which an array of solid state disks (SSDs) that is external to the DAS controllers of the DAS system is used by the DAS controllers as WB cache memory for performing WB caching operations. Using the external SSD array as WB cache memory allows the DAS system to be fully cache coherent without significantly increasing the complexity of the DAS system and without increasing the amount of bandwidth that is utilized for performing caching operations. In addition, using the external SSD array as WB cache memory obviates the need to mirror DAS controllers.

Abstract: At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.

Abstract: A device and method for retrofitting a light fixture from use with a lamp socket that employs an incandescent or metal halide lamp, to use with another lamp assembly. The lamp fixture has a collar with a base and an annular outer wall extending out from the base. The LED lamp device includes a neck base having an annular outer wall having a shaped outside surface that is placed into direct surface contact with the inner surface of the annular outer wall of the collar, to establish an effective heat-transferring interface. The shaped outer surface of the neck base provides proper fitting of the LED lamp device into the lighting fixture, and provides a heat-transferring interface over substantially all of the outer surface of the neck base, to dissipate heat away from the LED module. Aluminum material provides high thermal conductivity, light weight, availability, and low cost.

Abstract: Configurable power segmentation using a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer in an integrated circuit, and coupling a power region in the transistor layer to at least one power source based on a state of the nanotube structure. Nanotube material may be sputtered over a plurality of layers to form the nanotube structure. The nanotube structure may be curved to flex to a conductive surface when a current is applied to the nanotube structure. The power region may be coupled with at least two power sources that are concatenated together to provide cascaded current to the power region. One or more power regions in the integrated circuit may be enable based on the patterning the nanotube structure and the coupling of the power region to at least one power source.

Abstract: A computer implemented method, apparatus, and computer usable program code are provided for managing dual active controllers in a high availability storage configuration. Redundant dual active controllers in high availability storage configurations are made to appear as individual storage target devices to a host system. Each controller owns certain volumes of data storage. When a host system sends a request to identify available data volumes, the controller that owns certain volumes provides preferred paths to those owned volumes. The host system may also send an inquiry to a controller that asks the controller about data volumes not owned by the controller. For such inquiries, no paths to the non-owned data volumes are returned to the host system.

Abstract: A method for designing an integrated circuit, comprising the steps of (A) calculating an efficiency value for each of a plurality of equivalent cells in the design; and (B) selecting a number of the plurality of equivalent cells based on the efficiency values. The equivalent cells (i) decrease an overall delay of a path to meet a timing specification, and (ii) minimize an increase in overall leakage current.

Abstract: A network is configured to charge fees at a first rate for transmitting data of a first type and fees at a second, less expensive, rate for transmitting data of a second type. In a first embodiment, at least a portion of the original data transmitted is converted from the first type into the second type before sending the processed data to the network. A corresponding conversion from the second type into the first type is performed at the receiver's side to obtain re-created data from the received data. In a second embodiment, the original data is processed to obtain at least a first portion of data having the first type and a second portion of data having the second type. The at least two portions are sent to the network via different channels ensuring that at least the second portion will be billed at the second, lower rate.

Abstract: Apparatus and methods for an enhanced bridge device for coupling multiple non-Fibre Channel storage devices to a Fibre Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.

Abstract: A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.

Abstract: A secure memory system and a method of maintaining the security of memory contents. One embodiment of the system includes: (1) a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place the system in a secure mode, (2) a secure memory bridge coupled to the security control and system memory and configured to encrypt and decrypt data associated with the system memory based on a state of the system memory secure mode signal and (3) a boot processor coupled to the security control module and the secure memory bridge and configured to transmit requests to the secure memory bridge in the secure mode and an unsecure mode.

Abstract: Apparatus and methods improved fair access to a Fibre Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.

Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.