Abstract: The present invention is a Battery Backup Unit (BBU) Assembly. The BBU Assembly may include a Printed Circuit Board (PCB). The BBU Assembly may further include a protection circuit connected to the PCB. The BBU Assembly may further include a battery pack connected to the PCB. The battery pack may include a plurality of Lithium-ion (Li-ion) cells. The battery pack may be configured as a 2-cell series stack, a 3-cell series stack, or a 4-cell series stack. The BBU Assembly is configured for electrically connecting the battery pack to the protection circuit.

Abstract: A method for modulating a video input signal received into a modulation circuit is disclosed. A first step of the method generally comprises (A) during a first modulation pass, generating (i) a primary frame by inserting a plurality of primary synchronization codes into the video input signal, (ii) a secondary frame by inserting a plurality of secondary synchronization codes into the video input signal, (iii) a plurality of first values and a first digital sum value both for the primary frame and (iv) a plurality of second values and a second digital sum value both for the secondary frame. A second step of the method generally comprises (B) during a second modulation pass, generating a video output signal presented from the modulation circuit by modulating the video input signal using one set of (i) the first values and (ii) the second values as determined by the first digital sum value relative to the second digital sum value.

Abstract: A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

Abstract: Methods and systems are provided for managing power allocation to a SAS target coupled with a SAS initiator through a SAS expander. The expander exchanges messages with the target to manage the power allocation to the target. The target transmits a power request message through the expander to the initiator. In some embodiments, the initiator transmits a power request received message to the expander. The expander may then transmit a power grant message to the target in response to receiving the power request received message. In other embodiments, the expander monitors the messages transmitted from the target to the initiator. The expander may then transmit a power grant message to the target in response to the expander monitoring the power request message.

Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.

Abstract: Methods and systems for distributing I/O requests from a computer system to a storage system over multiple paths having non-homogeneous transfer speeds. A large I/O request is partitioned into a plurality of smaller I/O operations between a computer system and a storage system. The I/O operations are distributed over a plurality of communication paths coupling the computer system and the storage system. The distribution attempts to balance the load over the multiple paths based on the transfer speed of each path. In one embodiment, operations are distributed only to the highest speed paths presently operable. In another embodiment, an estimated completion time for an operation is determined for each path and a path with the lowest estimated completion time is selected to transfer the next operation.

Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Abstract: Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ? of a 1× DDR3 clock period.

Abstract: Methods and systems for automatically identifying storage array modifications thereof. An interface device associated with a data-processing system and a storage array thereof can be automatically monitored in order to identify one or more command completion events associated with the interface device. Data indicative of the status of the interface device can then be automatically compiled in response to identifying the command completion even(s) as a result of automatically monitoring the interface device. Data indicating that the storage array has been modified can thereafter be generated if the data indicative of a status of the interface device is equivalent to a particular value.

Abstract: A method of switching a plurality of tributaries disposed among a plurality of time slots in a frame is disclosed. The method generally includes the steps of (A) buffering the frame, (B) switching the tributaries among the time slots in response to a read address and (C) generating the read address in response to a plurality of identifications in a connection map, the connection map defining (i) at most one of the identifications for each of the tributaries and (ii) one of the identifications for each of the time slots carrying other than the tributaries.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.

Abstract: To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device.

Abstract: An electronic pressure-sensing device 100 comprising a transistor 105 located on a substrate 110. The device also comprises a linker arm 115 that has a tip 120 which is configured to touch a contact region 125 of the substrate that is near the transistor. The device also comprises a pressure converter 130 that is mechanically coupled to the linker arm. The pressure converter is configured to cause, in response to a pressure change, the tip to impart a force capable of changing an electrical conductivity of the transistor.

Abstract: An apparatus generally having a reference memory and a motion estimation circuit is disclosed. The reference memory may store reference samples used in a motion estimation of a current block beyond a boundary of a picture. The motion estimation circuit may (i) buffer the reference samples as copied from the reference memory, the reference samples as buffered residing both (a) inside the boundary and (b) inside a search window of the motion estimation, (ii) shift a sub-set of the reference samples to align with a corner of a sub-window, the sub-window being (a) completely within the search window and (b) at least partially outside of the boundary, (iii) fill an empty portion of the sub-window with copies of the reference samples within the sub-set and (iv) generate difference values by comparing the current block against the reference samples within the sub-window a plurality of times.

Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.

Abstract: An instrument is provided having a shaft extending to a distal end having a cavity, and a passageway extending to the cavity through which a first suture end of a suture loop extends from a tissue site to facilitate a user looping a second suture end around the first suture end between the tip and the site to form a knot. Advancing of the distal tip while drawing the first suture end through the passageway pushes the knot to the site. The distal tip of another embodiment adds another passageway through which the second suture end is passed to assist in forming and pushing a knot at to the tissue site. The distal end has two openings through which two suture ends are passed from the placed knot, and a blade in the distal end is positionable to cut the suture ends near the knot.

Abstract: The present invention is a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may establish the alternative path for communication but may not use it as long as there is an I/O Path available. In the present invention, two types of P2P calls, such as event notification calls and cluster operation calls may be supported.

Abstract: A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

Abstract: Disclosed is a common mode feedback circuit for a differential amplifier that eliminates the effects of low frequency noise. A modulator is placed in a common mode feedback loop that modulates the feedback loop signal at a predetermined frequency to up-convert the low frequency noise. The predetermined frequency may be selected to be above the operating range of the downstream circuitry. In addition, a low pass filter can be used to eliminate the up-converted noise.