Abstract: An integrated computational and communication system having modular components, a framed user interface and a method of operation an integrated computational and communication system are provided. In one embodiment, the integrated computational and communication system includes: (1) an input component configured to receive input data from a user, (2) an output component configured to provide output data to the user, (3) a controller configured to provide computational functionality and telephone communication for the system and (4) a communication base station configured to provide bi-directional communication channels between the input and output components, the communication base station and the controller, wherein the communication base station and the controller are adapted to be worn by the user.

Abstract: An apparatus including a parsing circuit and a control circuit. The parsing circuit may be configured to generate a plurality of decoded syntax elements in response to (i) a serial bitstream and (ii) a control signal. The control circuit may be configured to generate the control signal in response to the plurality of decoded syntax elements. The parsing circuit may generate the plurality of decoded syntax elements by grouping syntax elements for atomic decoding such that each (i) one or more consecutive syntax elements without context information relevant to the decoding and (ii) a non-zero syntax element presented at the end of each group.

Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract: A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: A method for demodulating a tracking error signal comprising the steps of (A) demodulating the tracking error signal when starting motion, (B) demodulating the tracking error signal after motion has started, and (C) demodulating the tracking error signal before and after lens motion stops.

Abstract: An optical-disc player having a reader and a controller. The reader derives out-of-band information from surface marks of an optical disc, where the controller controls operations of the reader based on the derived information. The controlled operations may involve the reading and rendering of embedded data of the optical disc. For example, a person writes the words “Spanish” and “widescreen” on the surface of a DVD with a marker and inserts the DVD in a DVD player. The DVD player scans the surface of the DVD and sends the resulting image data to an optical character recognition (OCR) module. The OCR module outputs a text file containing the words “Spanish” and “widescreen” to a controller (e.g., Microsoft HDi runtime). In response, the controller sets the playback language to Spanish and the screen format to widescreen.

Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Abstract: Methods and systems for support a unified Web Based Enterprise Management (“WBEM”) solution is provided. A first processing element for generating first HTTP content data is provided such that a response to a non-Common Information Model (“CIM”) request is based on the first HTTP content data. A second processing element for generating second HTTP content data is also provided such that another response to a CIM request is based on the second HTTP content data. At least one of the first processing element and the second processing element is accessible directly only from within the system to unify access to the two elements.

Abstract: Thermal control through a channel structure is disclosed. In one embodiment, an apparatus includes devices operable at an undesired temperature relative to a desired operating temperature, a vented cover of each of devices, and a channel structure formed along a side face of each of the devices, the channel structure having any number of ridges to transfer a gas between the vented cover and an external location to the apparatus. The gas may modify an operating state of the devices from the undesired temperature to the desired operating temperature. A heat structure coupled to the vented cover and the side face may absorb a portion of an energy dissipated by at least one of the devices. A printed circuit board may be formed along an opposite face relative to the vented cover to enable the gas to escape to the external location through a cavity of the apparatus.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.

Abstract: A CAD tool that supports an overlay-enabling operating mode. After the overlay-enabling operating mode is entered, the layout-editing facility permits modifications to the interconnect structure of an integrated circuit that is being designed regardless of whether a particular modification interferes with an existing pattern of metal fill. For example, a new signal wire can be added to electrically connect two specified points in the layout in a manner that causes the wire to cross over one or more metal-fill tiles. The CAD tool then modifies the fill pattern to get rid of any design-rule violations caused by the modifications to the interconnect structure by removing and/or modifying one or more fill tiles.

Abstract: Methods and apparatuses are provided for active-active support of virtual storage management in a storage area network (“SAN”). When a storage manager (that manages virtual storage volumes) of the SAN receives data to be written to a virtual storage volume from a computer server, the storage manager determines whether the writing request may result in updating a mapping of the virtual storage volume to a storage system. When the writing request does not involve updating the mapping, which happens most of the time, the storage manager simply writes the data to the storage system based on the existing mapping. Otherwise, the storage manager sends an updating request to another storage manager for updating a mapping of the virtual storage volume to a storage volume. Subsequently, the storage manager writes the data to the corresponding storage system based on the mapping that has been updated by the another storage manager.

Abstract: Storage array operations, such as code downloads and other operations of the type that cause loss of access to portions of the storage array, are managed in a manner that preserves access to other portions of the storage array so that other storage array operations, such as data synchronization, can continue.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter ? and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on ?, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of ? = 2 B - A 2 B and D>i?0 and 2C>j?0, where B?0, 2B>A>0, C?1 and D?1, and magnitude s i , j = 1 - ? i + ? i · 1 - ? 2 C · j ? ? or ? ? s D - 1 , j = 1 - ? D - 1 + ? D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on ? and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SAS standard and causing communication between one or more hosts and a SATA/SAS device. The communication system includes a multi-port bridge device including two or more SAS ports through which the bridge device communicates to hosts. The multi-port bridge device further includes a SATA port through which the bridge device communicates to a SATA device, each said SAS ports having associated therewith addresses for identifying the ports, the bridge device operative to generate addresses unique to each SAS port and operative to communicate the port addresses, through a SAS frame, wherein identification of SAS ports is achievable even when the SATA device is inoperational.