Abstract: A method for a color tone correction is disclosed. The method generally includes the steps of (A) generating a plurality of first intermediate components by scaling a plurality of first color components towards a first ideal color, wherein the first color components (i) are for a first plurality of pixels in an input video signal and (ii) fall inside a first region of a color space, (B) generating a plurality of first corrected components by adjusting the first intermediate components such that a first mapping of the first color components to the first corrected components is both (i) continuous in the color space and (ii) non-overlapping in the color space and (C) generating an output video signal by combining the first corrected components with a plurality of unaltered color components, wherein the unaltered color components (i) are for a second plurality of the pixels and (ii) fall outside the first region.

Abstract: An apparatus comprising a video decoder, a video memory and a global motion circuit. The video decoder may be configured to generate a decoded video signal in response to a coded video signal. The video memory may be connected to the video decoder. The global motion circuit may be configured within the video decoder circuit. The global motion circuit may be configured to (i) receive one or more warp points and (ii) generate one or more warping addresses presented directly to the video memory.

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract: Systems and methods are disclosed for the intelligent lighting of large areas and structures such as parking garages. Ultrasonic distance measuring sensors can be used to obtain occupancy data for the area or structure, such as a parking garage, and to control the intensities of the individual lights in the system for energy conservation. Persons in the area, e.g. parking their cars, can be shown the path to the exit by specific preset intensity level and/or color of light. In parking garage embodiments, persons in the process of parking their cars are shown the empty spots by lights of a specific intensity and/or color. The addition of passive infrared motion detectors enables the system to illuminate the area around a moving person, and alarm if a person is behaving unexpectedly. A controller can communicate with sensors and/or lighting elements by wireless or wire (cable) communication.

Abstract: Disclosed are lighting techniques, including systems, apparatus, and methods, that employ optical transmission of two-dimensional control signals to manipulate lighting elements. The lighting apparatus can include a projector with an IR LED array to wirelessly transmit pixel information onto a target space. The pixel information controls lighting elements within the target space. The two-dimensional control signals can includes subareas corresponding to lighting elements in a control array. The lighting elements can be lights of desired wavelengths including infrared and/or visible wavelengths. LEDs can be used as light sources in exemplary embodiments.

Abstract: Disclosed are lighting techniques, including systems, apparatus, and methods, that employ optical transmission of two-dimensional control signals to manipulate lighting elements. The lighting apparatus can include a projector with an IR LED array to wirelessly transmit pixel information onto a target space. The pixel information controls lighting elements within the target space. The two-dimensional control signals can includes subareas corresponding to lighting elements in a control array. The lighting elements can be lights of desired wavelengths including infrared and/or visible wavelengths. LEDs can be used as light sources in exemplary embodiments.

Abstract: A method for processing a transport stream is disclosed. The method generally comprises the steps of (A) parsing the transport stream to separate a transport packet, (B) generating a plurality of status items for the transport packet, (C) writing a relevant portion of the transport packet and the status items together in a memory and (D) reading the relevant portion of the transport packet and the status items from the memory for post-parsing processing of the transport packet based upon the status items.

Abstract: The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. The method further includes swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static. The method further includes regenerating a DQS (Data Strobe Signal) clock.

Abstract: An apparatus comprising an input circuit, a content analyzer, a storage circuit and an output circuit. The input circuit may be configured to generate a first intermediate signal from a plurality of input video signals. The content analyzer circuit may be configured to present one or more flags in response to the intermediate signal. The storage circuit may be configured to (i) store and organize the first intermediate signal into a plurality of sequences each related to one of the input video signals and (ii) generate a second intermediate signal from the sequences. The output circuit may be configured to generate an output video signal in response to the second intermediate signal. The output circuit may be configured to embed tracking information into the output video signal in response to the one or more flags.

Abstract: Systems and methods for allocating assets to a plurality of devices are presented. In one embodiment, devices may be communicatively connected to one another through a device loop. Each device may be configured for determining a portion of an asset that it will use. A controller may also be communicatively connected to the communication medium and configured for determining a capacity of the asset. The controller may transfer control information to the devices so as to allocate the asset to the devices based on the capacity of that asset. In another embodiment, each of the devices may be communicatively connected directly to the controller rather than to one another.

Abstract: A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.

Abstract: System and methods are disclosed for gathering debug information of a storage system of a computer system without requiring additional external hardware directly connected to the controller of the storage system.

Abstract: Methods and apparatuses for improving detection of a Serial Advanced Technology Attachment (“SATA”) target device by a storage initiator over a link. The storage initiator receives a Frame Information Structure (“FIS”) and determines whether the FIS is valid. In direct response to a determination that the FIS is invalid, the storage initiator immediately resets the link to the SATA target device.

Abstract: A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.

Abstract: The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.

Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.

Abstract: A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

Abstract: A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.

Abstract: A method for processing a video stream is disclosed. The method generally includes the steps of (A) checking a respective first motion vector for each of a plurality of blocks in a group within an inter-coded picture of the video stream, (B) loading first motion compensation data for the group from a memory to a motion compensation process in a first bus transfer in response to all of the blocks in the group having both (i) a same first reference frame and (ii) a same first motion vector in at least one of a reference picture list 0 and a reference picture list 1 and (C) reconstructing the blocks from the first motion compensation data and the same first motion vector.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.