Patents Assigned to LSI
  • Apparatus and methods for improved SATA device interaction without a SAS expander
    Patent number: 7814245
    Abstract: Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: October 12, 2010
    Assignee: LSI Corporation
    Inventor: Steven A. Schauer
  • System for automatic bandwidth control of equalizer adaptation loops
    Patent number: 7813415
    Abstract: A method to reduce peak power consumption during adaptation for an integrated circuit (IC) with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: October 12, 2010
    Assignee: LSI Corporation
    Inventors: Ephrem C. Wu, Ye Liu, Freeman V. Zhong
  • CONFIGURABLE STORAGE ARRAY CONTROLLER
    Publication number: 20100257301
    Abstract: A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Applicant: LSI CORPORATION
    Inventors: John R. Kloeppner, Jeremy D. Stover, Dennis E. Gates, Jason M. Stuhlsatz, Robert E. Stubbs, Mohamad El-Batal
  • System for integrity protection for standard 2n-bit multiple sized memory devices
    Patent number: 7809899
    Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: October 5, 2010
    Assignee: LSI Corporation
    Inventors: Eskild T Arntzen, Jackson L. Ellis
  • COMPUTER STORAGE APPARATUS FOR MULTI-TIERED DATA SECURITY
    Publication number: 20100250602
    Abstract: A computer storage apparatus. In one embodiment, the apparatus includes: (1) primary file storage, (2) a controller coupled to said primary file storage and configured to provide an interface by which data is communicated therewith, (3) formula/offset file storage coupled to said controller and configured to store at least one formula/offset and (4) pointer file storage coupled to said controller and configured to store at least one pointer, said controller further configured to provide said interface based on interaction with said formula/offset file storage and said pointer file storage.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventor: Lloyd W. Sadler
  • SYSTEM FOR DATA SECURITY USING USER SELECTABLE ONE-TIME PAD
    Publication number: 20100246817
    Abstract: A method of generating a key, a method of encrypting a message and an encryption/decryption system. In one embodiment, the method of generating the key includes: (1) selecting a common document to serve as a one-time pad, (2) generating a pointer, (3) searching the common document based on the pointer and (4) retrieving a key from the common document.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventor: Lloyd W. Sadler
  • BUS ARBITRATION SYSTEM, A METHOD OF CONNECTING DEVICES OF AN IC EMPLOYING A BUS SYSTEM AND AN IC
    Publication number: 20100250808
    Abstract: A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventor: Balaji Govindaraju
  • METHODS AND SYSTEMS FOR CONTROLLING ELECTRICAL POWER TO DC LOADS
    Publication number: 20100244929
    Abstract: Fixed Frequency, Fixed Duration power controls methods and systems are described for application of power to electrical loads. FFFD techniques according to the present disclosure utilize power train pulses with fixed-frequency fixed-duration pulses to control power applied to a load. The load can be any type of DC load. FFFD techniques allows for controlled variation of the fixed length of the ON pulse, the Fixed length of the OFF or recovery period, the total time period for one cycle, and/or the number of pulses in that time period. Applications to electric motors, electric lighting, and electric heating are described. Related circuits are also described.
    Type: Application
    Filed: May 13, 2010
    Publication date: September 30, 2010
    Applicant: LSI INDUSTRIES, INC.
    Inventors: Bassam D. Jalbout, Brian Wong
  • Data Volume Rebuilder and Methods for Arranging Data Volumes for Improved RAID Reconstruction Performance
    Publication number: 20100251012
    Abstract: A data volume rebuilder reduces the time required to reconstruct lost data in a RAID protected data volume operating with a failed physical disk drive. A data volume rebuilder uses the remaining functioning physical disk drives in the RAID protected data volume operating with the failed disk to regenerate the lost data and populate a virtual hot spare store allocated in a separate RAID protected data volume. The recovered data is distributed across the physical disk drives supporting the virtual hot spare store. Once the virtual hot spare store is populated, the data volume can recover from a subsequent failure of a second physical disk drive in either RAID group. After replacement of the failed physical disk drive, the data volume rebuilder moves the recovered data from the virtual hot spare store to the new physical disk drive.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: LSI CORPORATION
    Inventors: Ross E. Zwisler, Brian D. McKean
  • DYNAMIC LOAD BALANCING OF FIBRE CHANNEL TRAFFIC
    Publication number: 20100247094
    Abstract: Systems and methods herein provide for load balancing Fibre Channel traffic. In this regard, a Fibre Channel load balancer may be operable to monitor Fibre Channel paths coupled to a host bus adapter and determine the speeds of the Fibre Channel ports within the Fibre Channel paths. The Fiber Channel load balancer may also be operable to determine certain characteristics of the Fibre Channel traffic being passed over the Fibre Channel paths. For example, a load balancer may determine Fibre Channel traffic sizes of pending requests and, based in part on the traffic sizes and operable normalized speeds of the Fibre Channel ports, adaptively route the pending original traffic across the Fibre Channel ports.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Applicant: LSI Logic Corp.
    Inventor: Howard Young
  • DEVICE FOR DATA SECURITY USING USER SELECTABLE ONE-TIME PAD
    Publication number: 20100250968
    Abstract: Devices for securing data and method of managing a one-time pad stored in nonvolatile memory of a device. In one embodiment, the device for securing data includes: (1) a nonvolatile memory, (2) a nonvolatile memory controller coupled to the nonvolatile memory and configured to cooperate with the nonvolatile memory to make a key available when a password provided to the device is valid and (3) a self-destruct circuit coupled to the nonvolatile memory and configured to corrupt at least part of the nonvolatile memory when the password is invalid.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventor: Lloyd W. Sadler
  • THREE-DIMENSIONAL ELECTRONICS PACKAGE
    Publication number: 20100244276
    Abstract: An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventors: Jeffrey P. Burleson, Shahriar Moinian, John Osenbach, Jayanthi Pallinti
  • SYSTEMS AND METHODS FOR INFORMATION SECURITY USING ONE-TIME PAD
    Publication number: 20100246811
    Abstract: A method of verifying a password and methods of encryption and decryption using a key generated from a one-time pad. In one embodiment, the method of verifying includes: (1) receiving a password attempt, (2) retrieving a pointer from memory, (3) searching a one-time pad based on the pointer to retrieve a password, (4) comparing the password attempt with the password and (5) generating a new pointer if the password attempt matches the password.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventor: Lloyd W. Sadler
  • Methods and structures for testing SAS transceiver training options in SAS-2 training windows
    Patent number: 7805554
    Abstract: Method and structures provide for testing a SAS link in association with participating in training windows to determine success/failure in using a negotiated speed using one or more configured sets of transceiver training options. For each device linked to a master SAS device, each possible set of transceiver training options is configured and one or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred set of transceiver training options for communication between the master device and that attached device. The transceiver training options to be varied and tested may include: amplitude, slew rate, de-emphasis, and spread spectrum clocking.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: September 28, 2010
    Assignee: LSI Corporation
    Inventors: David T. Uddenberg, Gabriel L. Romero
  • Optimized reconstruction and copyback methodology for a disconnected drive in the presence of a global hot spare disk
    Patent number: 7805633
    Abstract: The present invention is a system for optimizing the reconstruction and copyback of data contained on a failed disk in a multi-disk mass storage system. A system in accordance with the present invention may comprise the following: a processing unit requiring mass-storage; one or more disks configured as a RAID system; an associated global hot spare disk; and interconnections linking the processing unit, the RAID and the global hot spare disk. In a further aspect of the present invention, a method for the reconstruction and copyback of a disconnected RAID disk utilizing a global hot spare disk is disclosed. The method includes: disconnecting a RAID component disk; reconstructing data from the disconnected RAID disk onto a global hot spare disk; reconnecting the disconnected RAID component disk; and copying the reconstructed data from the global hot spare disk back to the reconnected RAID component disk.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: September 28, 2010
    Assignee: LSI Corporation
    Inventors: Satish Sangapu, Kevin Kidney, William Hetrick
  • Wire bond integrated circuit package for high speed I/O
    Patent number: 7804167
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 28, 2010
    Assignee: LSI Logic Corporation
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • N+1 Protection Using a Processor-Based Protection Device
    Publication number: 20100238794
    Abstract: In an N+1 protection scheme for a router in a data or telecommunications network, a processor-based protection unit has a replica device handle, corresponding to each of the N working units, stored in the protection unit's local memory. Each replica device handle is an image of the connections provided by the corresponding working unit. In one implementation, upon detection of a failure of one of the working units, the router's controller unit sends a single command to instruct the protection unit to reconfigure itself using the corresponding locally stored replica device handle to assume the routing functions of the failed working unit.
    Type: Application
    Filed: August 12, 2009
    Publication date: September 23, 2010
    Applicant: LSI CORPORATION
    Inventors: Vijayalakshmi Kanthamneni, Ravi Krishnaswamy, Ning Li, Donna M. Nemshick, Tim Reinhard, Steven Rothweiler, Robert L. Smigielski, Martin Trew, Swaminathan Venkatakrishnaprasad, Wen Wang, Jay P. Wilshire
  • HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP
    Publication number: 20100238938
    Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 23, 2010
    Applicant: LSI CORPORATION
    Inventors: Ting Zhou, Sheng Liu, Ephrem Wu
  • HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT
    Publication number: 20100238937
    Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 23, 2010
    Applicant: LSI CORPORATION
    Inventors: Ting Zhou, Sheng Liu, Ephrem Wu
  • ALLEVIATING BLOCKING CASES IN A SAS SWITCH
    Publication number: 20100241779
    Abstract: A first SAS expander including at least two phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.
    Type: Application
    Filed: June 1, 2010
    Publication date: September 23, 2010
    Applicant: LSI CORPORATION
    Inventors: Stephen B. Johnson, Christopher McCarty