Abstract: A comparator receives first differentials, compares the differentials to a positive offset, and sets bits dependent upon whether the differentials are greater than the positive offset. The comparator receives second differentials, compares the differentials to a negative offset, and sets bits dependent upon whether the differentials are greater than the negative offset. The comparator compares the first bits to the second bits, and sets a mask dependent upon whether the first bits and the second bits are identical. The comparator receives subsequent differentials, compares the differentials to a zero offset, and sets bits dependent upon whether the differentials are greater than the zero offset. The subsequent bits are compared to the mask and corrected.

Abstract: A method for video decoding is disclosed. The method generally includes the steps of (A) decoding a first picture from a bitstream, the first picture having a first resolution, (B) storing the first picture at the first resolution in a memory and (C) storing the first picture at a second resolution in the memory, wherein the second resolution is lower than the first resolution.

Abstract: Incorporation of a sensor, such as an optical or laser based sensor, into a wafer edge processing unit, such as a WEE unit or mechanism. This sensor enables the WEE unit to be referenced to the wafer edge. Specifically, the sensor can be used to place a WEE unit in a fixed but accurate location at the beginning of the wafer edge expose process. Another approach is to have the WEE drive controller actively follow the edge of the wafer as it rotates during the WEE process, which has the advantage of compensating for any wafer centering errors as well as diameter and placement errors. In yet another approach, the edge sensor is used to sense and track the edge of a previous layer WEE pattern. The sensor can also facilitate the measuring of a distance from a wafer edge to a WEE edge feature.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: Disclosed is an adaptive method for training a source synchronous parallel receiver. The adaptive method for training, or aligning, parallel data channels permits a parallel communication receiver to adaptively adjust the timing of data channels to align the data channels with a frame channel and achieve a source synchronous signal for the parallel data channels. Further, portions of the frame channel training pattern may be used because possible time shift accuracy error is accounted for between the communication channels and a determination is made as to which portion of the frame pattern is currently being received. The data channels are then aligned appropriately.

Abstract: A logic built-in self-test (LBIST) module and a method of online system testing. In one embodiment, the LBIST module includes: (1) first and second data sources selectable to provide alternative respective first and second data to at least one scan chain and (2) a scan clock modifier associated with the first and second data sources and configured to drive the at least one scan chain with a selectively aperiodic modified scan clock signal.

Abstract: A lighting assembly comprises a body and at least one socket mount pivotably mounted to the body and at least one socket removably secured to the socket mount; the socket mount pivotable between first and second socket mount orientations in which the socket is at least partially located within the body channel in the first socket mount orientation and at least partially located outside the channel in the second socket mount orientation.

Abstract: Modular light source are described with polarized states and a video screen including a matrix of the modular light sources. Each modular light source may constitute a pixel of the screen. Each pixel may be controlled to emit light in a polarized state. As a result, the screen may generate images with different polarities at any pixel, at any time, in addition to generating non-polarized pixels or images if desired. Using a viewing device, such as glasses, having a lenses with different polarization characteristics, a viewer may perceive an image generated by the screen as having three dimensions. Related methods and computer program products are also described.

Abstract: Screens for three-dimensional (3D) viewing are described that can include a plurality of light sources used as a video screen in conjunction with a switching polarization filter or panel. The polarization panel can be used to synchronize the left and right views interleaved on the screen. Separate left and right video signals can be interleaved into a single continuous digital video signal, for example a DVI signal, which can be displayed by the video screen. By switching the polarization panels in front of the video screen in synchronization with the interleaved data, the images can be directed to the left and right eye of a viewer. A processor can be used to accomplish the interleaving of the signals while providing the necessary synchronization signal for the polarizing screen. Related methods are also described. The light sources can include LEDs, plasma screen, LCD screen, and spatially discrete sub groups of such.

Abstract: A latch for retaining moving parts on an enclosure service module (ESM) is provided. This latch comprises a retaining groove in the latch that holds a self-clinching standoff fastener attached to the ESM. A return spring is contained within a molded cavity in the latch, and an alignment groove in the latch is placed at one end of the return spring. The alignment groove guides an alignment pin on the ESM into a secure position, and the return spring applies pressure against the pin while the pin is in the alignment groove.

Abstract: The detector includes a plug for connecting a personal computer through a cable, a battery power supply which provides a constant power supply, and an MCU which receives a specific potential from the personal computer when the latter is connected.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.

Abstract: A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an accessed one of the controller circuits and one of a plurality of first busses. The arbiter circuit may be configured to control access to the controller circuits by the line buffer circuits.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

Abstract: An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.

Abstract: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Abstract: In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

Abstract: The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.

Abstract: Compressing state transition instructions may achieve a reduction in the binary instruction footprint of a state machine. In certain embodiments, the compressed state transition instructions are used by state machine engines that use one or more caches in order to increase the speed at which the state machine engine can execute a state machine. In addition to reducing the instruction footprint, the use of compressed state transition instructions as discussed herein may also increase the cache hit rate of a cache-based state machine engine, resulting in an increase in performance.