Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.

Abstract: Various apparatuses and methods for a preferentially cooled electronic device are disclosed herein. For example, some embodiments provide an electronic apparatus including a package substrate and with a semiconductor die electrically and thermally connected to the package substrate by a plurality of connection nodes. At least one thermal trace interconnects at least one subset of the plurality of connection nodes. At least one heat dissipation trace on the package substrate is connected to the at least one subset of the plurality of connection nodes.

Abstract: A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.

Abstract: Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then applied to the zone permission table to determine the zoning permission for forwarding the frame through the expander. Pipelined logic within the expander sequences the operations of the memory circuit and the zone permissions table to account for clock cycle delays in processing of each. In one exemplary embodiment, the memory circuit is a content addressable memory (CAM). In another exemplary embodiment, the CAM also includes port routing information.

Abstract: Methods and microprocessors are provided for continuing execution of an instruction, even though execution of the instruction depends on a value of a conditional bit (e.g., a flag bit or a predicated bit) that has not been determined. Rather than stalling execution of the instruction, a predicted value of the conditional bit is predicted and execution of the instruction is continued based on the predicted value of the conditional bit. If the predicted value matches a determined value of the conditional bit, a result from continuing execution of the instruction is committed. An existing branching prediction block of a microprocessor might be extended to support this mechanism.

Abstract: An apparatus and method for enabling a circuit board or data storage module located within a slot in an enclosure to determine the identification of the slot by detecting a characteristic feature of the slot. In this manner the circuit board or data storage module can be instructed to operate in accordance with the function of that slot. This is important when a plurality of slots having different functions contains identical circuit boards or modules.

Abstract: An embodiment of the present invention includes a switch employed in a system having two hosts and a device and for coupling two or more host ports to a device. The switch includes a power signal control circuit generating a power signal for use by the device in receiving power for operability thereto, the power signal control circuit responsive to detection of inoperability of the device and in response thereto, toggling the power signal to the device while avoiding interruption to the system.

Abstract: A method for obscuring data and software including the steps of (A) generating code for performing a predefined operation using one or more sets of predefined data, (B) generating a first binary representation of the code and (C) mixing the one or more sets of predefined data into the binary representation of the code such that the one or more sets of predefined data and the code are substantially indistinct from each other.

Abstract: A therapeutic instrument for the ergonomic, effective and safe opening and closing of targeted remote tissue sites; includes a pistol grip style handle with a hand activated lever for needle deployment and, optionally, with features to control tissue cutting and guide wire installation; also incorporates a specialized elongated rigid or flexible instrument shaft, which enables vacuum assisted holding of tissue at a uniquely contoured distal tip, where placement of a suture in a purse string configures occurs along with, if desired, tissue cutting and guide wire passage.

Abstract: A therapeutic instrument for the ergonomic, effective and safe opening and closing of targeted remote tissue sites; includes a pistol grip style handle with a hand activated lever for needle deployment and, optionally, with features to control tissue cutting and guide wire installation; also incorporates a specialized elongated rigid or flexible instrument shaft, which enables vacuum assisted holding of tissue at a uniquely contoured distal tip, where placement of a suture in a purse string configures occurs along with, if desired, tissue cutting and guide wire passage.

Abstract: An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source.

Abstract: A plurality of memory circuits and a logic circuit. The plurality of memory circuits may be configured to store a plurality of pixels. The pixels may be used in a motion estimation stage of a video encoder. The logic circuit may be configured to (i) control which of the pixels are stored in which of the plurality of memory banks and (ii) control accessing of the plurality of pixels.

Abstract: An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.

Abstract: A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

Abstract: A method, computer program product, and queuing system for queuing prioritized items (such as network packets), which limits the degree to which higher-priority queue items are blocked by lower priority queue items, is disclosed. A preferred embodiment of the present invention uses a simple first-in-first-out (FIFO) queue as an input queue, along with an output queue corresponding to each packet priority. A strategy is applied at the output queues to guarantee that blocking of high-priority queue items in the input queue will be limited in duration. One disclosed strategy is to enforce a constraint that whenever an output queue of any priority becomes full, the output port will stop accepting packets of any priority until all queues have space for at least one packet of each priority. Another strategy is for the output port to stop accepting packets having priorities greater than or equal to the priority of the full queue.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.

Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.

Abstract: A method and a system for volume group creation based on an automatic drive selection scheme are disclosed. In one embodiment, a method of a redundant array of independent drives (RAID) includes processing at least one attribute data describing a volume group of the RAID. The method also includes automatically selecting a plurality of drives of the volume group based on at least one of an optimum tray distribution of the volume group, a spindle speed of each drive in the volume group, and an alignment of the plurality of drives in the volume group. In another embodiment, a system of a RAID includes a user device to communicate an attribute data describing a volume group of the RAID, and a drive selection module to automatically select a plurality of drives of the volume group based on the attribute data using a baseline selection algorithm.

Abstract: An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.