Abstract: Embodiments of the invention include a dictionary based data compression method, apparatus and system that is not based on either the LZ77 compression algorithm or the LZ78 compression algorithm, but includes many features of the LZW compression algorithm. The data compression method includes creating a mapping table of the messages in the alphabet of messages to a corresponding plurality of codewords, maintaining a dictionary including a mapping table of a first codeword and a second codeword to a new codeword, reading an input ensemble including a plurality of messages, converting the messages to an input codeword using the mapping table, and outputting the converted codewords as an output ensemble of compressed data. Unlike conventional data compression methods, the dictionary is generated from the output ensemble only, and is not based on any input messages. Therefore, the dictionary more quickly builds to define longer sequences of messages compared to conventional data compression methods.

Abstract: Embodiments of the invention include a device and method for improved battery learn cycles for battery backup units within data storage devices. The backup unit includes a first battery pack, a corresponding charge capacity gauge, one or more second battery packs, a corresponding charge capacity gauge, and a controller switch configured to select only one battery pack for a learn cycle at any given time. The charge capacity gauges are such that, at the end of the learn cycle discharge phase, the depth of discharge of the learn cycle battery pack is such that the charge capacity of the learn cycle battery pack combined with the full charge capacity of the remaining battery packs is sufficient for the device cached data to be off-loaded to a physical data storage device, and the data storage device does not have to switch from a write-back cache mode to a write-through cache mode.

Abstract: The present invention is directed to a method and system for detecting component level changes in a storage area network during power off state is provided. Storage profile changes may be utilized for monitoring components during a power cycle period of a storage array system coupled to a SAN. During the power on state of the storage array system, a storage profile (an on-power-storage profile) is collected and time stamped after predefined set of trigger points. Another storage profile (an off-power-storage profile) of the same storage array system may be collected immediately after a power cycle. The two versions of the storage profiles are compared immediately after the off-power-storage profile is created to determine whether the predetermined condition happened. A delta file may be generated after the comparison of the two versions of storage profiles. Each detected conditions may be logged in a log file of the storage array system.

Abstract: A method and/or a system of storage system management based on a backup and recovery solution embedded in the storage system is disclosed. A method of a storage system includes coordinating with a host system through a backup coordinator module embedded in the host system during at least one of a backup operation and/or a recovery operation associated with the host system, performing the at least one of the backup operation and/or the recovery operation associated with the host system using a backup and recovery module embedded in a controller firmware of the storage system. The method may include the backup and recovery module which interfaces with the host system through the backup coordinator module is agnostic to an operating system of the host system.

Abstract: The present invention is directed to a system and method for SAS PHY dynamic configuration which allows for attaching SAS devices having various width ports. Each PHY is configured to be a narrow port internally to the controller while PHYs for the attached device is configured to be a wide port externally to the controller. As such, new SAS devices may be attached without any external controller intervention to reconfigure PHYs to match the new SAS devices. The present invention may allow for the flexibility of designing a single initiator solution that can adapt to any number of SAS devices with any number of port widths. Additionally, the present invention allows for a single product to be released that can automatically adjust to a broad range of SAS solutions and SAS topologies.

Abstract: An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data on an output signal when in a first mode and memory data on the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.

Abstract: The present invention is directed to a method and apparatus for automatically tracking and communicating data storage device information using RF (radio frequency tags. An apparatus includes a data storage device and a RF tag attached to the data storage device, wherein the RF tag contains information about the data storage device. Using such an apparatus, assembling, selecting, logging and maintaining a data storage device may be done automatically.

Abstract: A system transforms data structures absent the need for a backup copy. The system transforms a first logical store in an initial logical arrangement to a desired logical arrangement where the data structures of the logical arrangements are different. The system uses a select sequence of data operations that moves data from its origin in the initial logical arrangement to a target location in the desired logical arrangement. The system generates and properly locates parity information when so desired. The system executes a subsequent data operation in accordance with an indication that the previous data operation was successful. Each subsequent data operation uses the source location from the previous data operation. A non-volatile memory element holds information concerning a present data operation to enable a rollback operation when a present data operation is unsuccessful.

Abstract: A controller coupled to a redundant array of inexpensive disks (RAID) includes a processor and a non-volatile memory element. The processor has an input/output port that is configurable in one of an open-drain driver configuration, a high-impedance driver configuration and a totem-pole driver configuration. The totem-pole driver configuration is capable of supplying sufficient current to operate a slave device coupled to the input/output port. Firmware stored in the non-volatile memory device dynamically adjusts the driver configuration to prevent negative voltage swings in a signal communicated via the input/output port.

Abstract: Lighting apparatus and structures are described that are adapted for installation in housings. The housings can be pre-existing ones, such as those installed for high-intensity discharge (HID) or other types of lighting. The lighting apparatus can include a light unit (e.g., luminaire) with desired type of light source(s), for example, an array of LEDs. The apparatus can include structures that are adapted for use with the housings such that installation of a light unit requires a minimum of user effort and time. Such lighting apparatus, and related installation methods, can accordingly provide for high-efficiency lighting. Related assembly and installation techniques are also described.

Abstract: An apparatus generally comprising a first circuit, a second circuit and a third circuit is shown. The first circuit may be configured to generate a phase signal by dividing each cycle of an output clock into a plurality of phase values. The second circuit may be configured to generate an intermediate data signal by interpolating an input data signal sampled with an input clock in response to the phase signal and the output clock. The third circuit configured to generate an output data signal by sampling the intermediate data signal with the output clock.

Abstract: A Pseudo Low Volume Reticle (PLVR) which consists of multiple design layers on a single reticle. Specifically, the reticle can include two instances of each layer in order to facilitate die-to-die inspection techniques. A scribe is wrapped around each instance of the layer, such that both the frame and active area of the chip can be inspected with the die-to-die method. The chip consists of design data for a given part. The scribe, or frame, is preferably standard data across products which is used for yield and in line testing during the chip manufacturing process. Since only one chip and scribe unit is necessary to manufacture a device at each layer, it is only necessary that one chip and scribe instance yield during the reticle manufacturing process.

Abstract: The present invention provides a method and an apparatus for providing data management between a serial interface and another component. A variable rate buffer manager and state machine progress data on a serial link relative to a width and clocking frequency of a parallel bus that interfaces within the serial link. Event scheduler logic is provided that controls the mode of operation of the buffer manager and state machine.

Abstract: A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.

Abstract: A method of partitioning storage is provided. In an exemplary embodiment, the method includes connecting at least one initiator with at least one target device. Upon connection of the at least one initiator with the at least one target device, at least one initiator-target association object may be created. The method may also include selecting at least one storage partition with the at least one initiator-target association object.

Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

Abstract: An embodiment of the present invention is disclosed to include a communication system configured to conform to SATA standard and causing communication between one or more hosts and a SATA device. The communication system, in accordance with one embodiment of the invention includes a multi-port bridge device having a command status manager (CSM) responsive to commands and status from one or more hosts and a data manager (DM) responsive to data from one or more hosts for buffering data substantially separately from that of commands and status.

Abstract: The present invention is a system utilizing multicast with distributed intelligence including an initiator device for transmitting a request, the request being addressed to a multicast group. The system also includes a switch for receiving the request from the initiator device. The switch is configured with multicast functionality for multicasting copies of the request to the multicast group. Additionally, the system includes a plurality of multicast group devices, each configured for receiving a copy of the request from the initiator device, via the switch. Each device of the plurality of multicast group devices is further configured with mapping functionality for allowing the storage device to determine a storage layout of the multicast group device. The initiator device, switch and each device of the plurality of multicast group devices are communicatively coupled via a network.

Abstract: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit.