Abstract: A data-processing system and method are disclosed, which generally includes a plurality of components connected to a bus within a data-processing apparatus utilizing one or more input/output interfaces (e.g., IOCTL) in communication with the bus. A dynamic interface is implemented, which includes a plurality of interface modules that permits varying data-processing applications to scan, identify and interface with the plurality of components utilizing the input/output interface, thereby increasing data-processing application development efficiency relative to one or more components within the data-processing system.

Abstract: An apparatus comprising an encoder, a packet generator, a disc loader, and a rebuild circuit. The encoder may be configured to generate a format data stream in response to an input signal. The packet generator may be configured to generate special packets from extracts of the format data stream. The disc loader may be configured to write the special packets on a disc. The rebuild circuit may be configured to (i) rebuild one or more navigation files and a file system with the special packets and (ii) write the one or more navigation files and the file system to the disc.

Abstract: A method and system of method and system of enhanced RAID level 3 is disclosed. In one embodiment, a method includes allocating three times a physical storage capacity of a data drive to a dedicated parity drive of a ‘n’ physical drives of a redundant array of independent disks, recovering n?1 physical drive failures of the ‘n’ physical drives through a parity-in-parity technique in which certain number of parities generated during an initial write of data may be physically stored and using an XOR function applied to the stored parities to recreate un-stored parities which enable recovery of the n?1 physical drive failures. The method may include creating a superior read/write access capability and/or a superior parity data redundancy through the mirroring. The method may also include recreating the un-stored parities after a time interval that may be specified by a user.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: The present invention is an optimized method for the rollback of copy-on-write snapshot volumes. A method in accordance with the present invention may comprise the following steps: (a) creating a copy-on-write snapshot volume; (b) receiving a base volume write request addressed to a base volume data block; (c) executing copy-on-write operations; (d) receiving a snapshot volume rollback request; (e) disabling the copy-on-write operations; and (f) executing volume copy operations.

Abstract: The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to two serial master devices, a synchronization logic capable of synchronizing the communications between one of the idle regenerators and a third idle regenerator coupled to the SATA disk drive. Furthermore the dual porting apparatus may include an auto detector capable of enabling either of the first two idle regenerators, thus effectively switching between the two.

Abstract: Structures and methods within an integrated circuit for controlling access to secured information embedded therein. A security block embedded within an integrated circuit (e.g., an SOC) may control authorized and unauthorized access to secured information stored within a memory of the integrated circuit. The security block may combine security key techniques and structures with a counting technique and structure such that when a maximum number of unauthorized attempts are detected, all further access to the secured information will be denied thereby rendering the IC unusable. In one aspect, the counting features may be implemented using a one time programmable register comprising a plurality of one time programmable bits such that each bit may be set to indicate detection of an unauthorized access attempt. If all bits of the OTP register are so set, the maximum number of unauthorized attempts has been detected and the circuit precludes all further access attempts.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: A method for composite noise filtering is disclosed. The method generally includes the steps of (A) generating a selection value in response to a stationary check identifying one of a plurality of blendings for a current item of a current field, (B) generating a filtered item in response to one of (i) a first of the blendings between the current item and a first previous item co-located in a first previous field having an opposite phase of composite artifacts from the current field and (ii) a second of the blendings between the current item and a first motion compensated item from the first previous field and (C) switching between the first blending and the second blending in response to the selection value.

Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: The present invention provides a method and system for reducing power consumption of a sound processor. Aspects of the invention include providing a sound processor access to at least one register having a plurality of bits corresponding to sound operations capable of being performed by the sound processor; and allowing a host processor to write a value to at least a portion of the plurality of bits in the register during sound processing to selectively disable individual operations performed by the sound processor.

Abstract: A method and apparatus is provided for determining thickness of films or layers during chemical-mechanical planarization/polishing (CMP) of a semiconductor substrate or wafer in situ. The method may be used to determine end-point during CMP especially of oxide films deposited on the substrate or wafer. In one embodiment, the method includes: a) capturing images of the surface of the substrate using high speed imaging; b) performing pattern recognition on the captured images; c) selecting one of the captured images based on the pattern recognition; and d) converting the selected image into a thickness measurement. In one form, the high speed imaging comprises a high speed camera, while in another form, the high speed imaging comprises a conventional camera and a laser pulse or flash tube. In yet another embodiment, reflective laser interference patterns of the substrate are captured and analyzed for interference pattern changes that can signal a practical end-point.

Abstract: An AC/DC power supply, a method of delivering DC power at multiple voltages and a computer data storage system. In one embodiment the AC/DC power supply includes: (1) a transformer having a primary winding couplable to an AC power source and a secondary winding inductively couplable to the primary winding and (2) multiple DC voltage rails coupled to the secondary winding at designated locations and configured to deliver power to loads coupled thereto, each of the DC voltage rails configured to dynamically transfer therebetween an available portion of the power in response to changes in the loads.

Abstract: Embodiments of the invention include a method, apparatus and system for storing data that involves storing boundary information for data that is being written to a plurality of data storage devices. The method includes storing boundary information for a write operation of data to a plurality of data storage device, writing the data to the plurality of data storage devices and removing the recorded boundary information upon completion of the write operation of the data to the plurality of data storage devices. The boundary information can indicate the data storage device regions where particular sets of data are to be written during the write operation. If an interruption occurs during the write operation, the boundary information can be used to recover from the interruption by identifying the specific data storage device region or regions where data was being written when the interruption occurred.

Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.

Abstract: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.

Abstract: Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.

Abstract: Described embodiments provide a method for calibrating a continuous-time filter having at least one adjustable parameter. A square-wave signal is filtered by a continuous-time filter having a cutoff frequency less than fs. The filtered signal is quantized at the rate fs. An N-point Fourier transform is performed of the quantized signal into N real output values and N imaginary output values. At least one of the real output values are accumulated to form a real output signal and at least one of the imaginary output values are accumulated to form an imaginary output signal. The real and imaginary output signals are summed to form an output signal, which is then squared. The squared output signal is compared to a comparison value. At least one parameter of the continuous-time filter is adjusted based upon the comparison. The steps are repeated until the squared output signal is approximately the comparison value.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.