Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.
Type:
Grant
Filed:
April 28, 2006
Date of Patent:
June 15, 2010
Assignee:
LSI Corporation
Inventors:
Ruben Salvador Molina, Jr., Alexander Tetelbaum
Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.
Abstract: A therapeutic instrument for the ergonomic, effective and safe opening and closing of targeted remote tissue sites; includes a pistol grip style handle with a hand activated lever for needle deployment and, optionally, with features to control tissue cutting and guide wire installation; also incorporates a specialized elongated rigid or flexible instrument shaft, which enables vacuum assisted holding of tissue at a uniquely contoured distal tip, where placement of a suture in a purse string configures occurs along with, if desired, tissue cutting and guide wire passage.
Abstract: The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.
Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
Type:
Grant
Filed:
April 17, 2007
Date of Patent:
June 1, 2010
Assignee:
LSI Corporation
Inventors:
Hao Cui, Peter A. Burke, Wilbur G. Catabay
Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager.
Abstract: An adapter card for directing an information handling system (or another device) device to copy one or more data packets buffered in its memory may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with the information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting a data packet between the electronic components and the information handling system device. The adapter card may buffer a data packet according to a particular interface format and/or may include a buffer for storing the data packet. The adapter card may include control logic configured to direct the information handling system device to copy the data packets buffered in the memory of the adapter card.
Abstract: The present invention enables assembly of drive boxes that stack drives more than one drive deep without requiring large numbers of PC boards or that the drive box to be pulled out of a rack to remove/replace the drives. A shielded multiple drive plug-in cable connects a single PC board to a plurality of drives in the drive box. The multiple drive plug-in cable provides power from the PC board to the drives and/or passes signal between the PC board and the drives. The multiple drive plug-in cable is configured to occupy a minimal cross-sectional area in order to maximize air flow within the drive box. The present invention reduces the cost of manufacturing the drive box, reduces EMI (electromagnetic interference), and prevents drops in signal integrity by reducing the number of PC boards required for a drive box.
Abstract: The present invention provides a method for reducing rebuild time on a Redundant Array of Independent Disks (RAID) device. A first stripe of the RAID device is selected. Write-back caching on a drive being built is enabled. Data and/or parity may be read from at least one other drive. The at least one other drive and the drive being built belong to a same stripe of the RAID device. When a RAID level of the RAID device is 5, the at least one of data or parity is XORed (exclusive ORed) to obtain a result. When the RAID level of the RAID device is 1, the at least one of data or parity is data and treated as the result. The result is written to a second drive, which is a repaired, replaced, or hot-spare drive for the drive being built.
Abstract: A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.
Type:
Grant
Filed:
December 21, 2005
Date of Patent:
May 18, 2010
Assignee:
LSI Corporation
Inventors:
Cristian Teodor Crisan, Ekambaram Balaji, David W. Vinke
Abstract: A video decoder comprising a first comfort noise addition block and a second comfort noise addition block. The first comfort noise addition block may be configured to (i) add comfort noise to luminance data and (ii) adjust a distribution of the comfort noise added to the luminance data. The second comfort noise addition block may be configured to (i) add comfort noise to chrominance data and (ii) adjust a distribution of the comfort noise added to the chrominance data. The first and the second comfort noise addition blocks may be integrated into a video output path of the video decoder. The distribution of the comfort noise added to the luminance data and the distribution of the comfort noise added to the chrominance data may be adjusted independently.
Abstract: Apparatus and methods are provided for managing SAS zone group permission tables using associated version identifiers. Zone group permission tables of a SAS domain may have associated version identifiers, indicating a version of the zone group permission table. The version identifier may be used to determine whether the zone group permission table is the same as the current version for the SAS domain without comparing the contents of the zone group permission table with the contents of the current version. The version identifier may also be used for determining which of a plurality of zone group permission tables of the SAS domain is the current version if two or more SAS zoning expanders are storing different zone group permission tables.
Abstract: The present invention provides a method for transmitting a non-SCSI command via a SCSI command. A CDB for the SCSI command is provided. The CDB includes bytes byte—0, byte—1, byte—2, . . . , byte_n, in which byte—0 includes an opcode for the SCSI command. An opcode for the non-SCSI command is loaded into byte—1. When the non-SCSI command is not greater than a fixed number of bytes, the non-SCSI command is loaded into at least one byte of the CDB, which includes byte—2. Data associated with the non-SCSI command is transmitted via a data phase associated with the SCSI command.
Abstract: LED lighting fixtures, or luminaires, related components, driver circuit, methods, and software/firmware are described can provide for among other things, ambient environment sensing, thermal self-monitoring, sensor-based power management, communications, and/or programmability. Driver and lighting circuits configured for electrical loads such as series arrangements of light emitting diodes are also described. Embodiments of PFC stages and driver stages can be combined for use as a power supply, and may be configured on a common circuit board. Power factor correction and driver circuits can be combined with one or more lighting elements as a lighting apparatus. Methods of hysteretic power factor correction start-up are also described.
Type:
Application
Filed:
October 20, 2009
Publication date:
May 13, 2010
Applicant:
LSI Industries, Inc.
Inventors:
Kevin Allan Kelly, John D. Boyer, Martin Brundage
Abstract: A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.
Abstract: A device may include a card including a card connector and/or a card edge lockshield disposed on at least a card connector first side. Additionally, a computer system may include a motherboard including at least one mating connector and/or at Least one card including a card connector and a card edge lockshield disposed on at least a card connector first side. Further, a method for providing the device and/or computer system is disclosed.
Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.
Type:
Grant
Filed:
November 2, 2005
Date of Patent:
May 11, 2010
Assignee:
LSI Corporation
Inventors:
Keith Grimes, Todd Jeffrey Egbert, Edmund Paul Fehrman
Abstract: A rack mount drive blade system having a chassis and a drive blade. The chassis has at least one blade bay to accept a drive blade, where the chassis accepts the drive blade into the blade bay with the drive blade in a horizontal orientation. Each blade bay has chassis to blade electrical contacts including at least one cable having a length, for making electrical connections between the chassis and the drive blade. Each blade bay also has slot portions for engaging the drive blade along a length of the drive blade. The chassis has at least one module bay to accept a shared resource module, where each module bay has chassis to module electrical contacts, for making electrical connections between the chassis and the shared resource module. The drive blade has a printed circuit board for providing electrical connections to and from components on the drive blade.
Type:
Grant
Filed:
July 3, 2008
Date of Patent:
May 11, 2010
Assignee:
LSI Corporation
Inventors:
Ryan S. Signer, John Dunham, Alan T. Pfeifer
Abstract: Systems and methods for reducing or eliminating use of read transactions by a message consuming device coupled through a shared bus to a message producing device to transfer a message from the producing device to the consuming device. Features and aspects hereof provide for use of only write transactions on the bus issued by the devices to transfer messages directly into the data memory of the consuming device. A memory manager on the producing device may manage allocation and freeing of buffer space within the data memory of the consuming device. The producing device notifies the consuming device when a message transfer is completed.
Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager.
Type:
Application
Filed:
October 30, 2008
Publication date:
May 6, 2010
Applicant:
LSI CORPORATION
Inventors:
Louis Henry Odenwald, JR., Roger Hickerson