Abstract: Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using end device grouping. A SAS end device grouping management application is configured to group SAS end devices, such as SAS initiator devices and SAS target devices, into any number of zones or zone configurations. The end device grouping application uses these defined zones to create a minimal number of zone groups, e.g., by creating one zone group per defined zone and populating the zone group with the ZPSDS entry point phys of the end devices in the zone from which the zone group is based, and to configure the respective permissions of the created zone groups. The end device grouping application then compares all existing zone groups for common phys and removes them to a new zone group. The zone groups are compared and processed in this manner until no zone groups have common phys.

Abstract: The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.

Abstract: A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.

Abstract: A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

Abstract: A method for film mode detection is disclosed. The method generally includes the steps of (A) detecting if a plurality of fields in a video signal are in a 3:2 pull-down pattern to control a plurality of first flags based on a plurality of statistics gathered from the fields, (B) detecting if the fields contain moving interlaced text to control a second flag based on both (i) the statistics and (ii) a repeat-field flag of the first flags that indicates repeating consecutive same polarity fields and (C) deciding among a plurality of inverse telecine processes to de-interlace the fields based on all of (i) a 3:2 mode flag of the first flags, (ii) a 3:2 direction flag of the first flags and (iii) the second flag.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: The link layer of the multi-root PCI (peripheral component interconnect) express device stores transaction layer packets (TLPs) sent from a transaction layer in a dedicated retry buffer dedicated to the virtual hierarchy (VH) associated with the TLP. The link layer of the multi-root device also stores information related to the TLP about the VH and an address of the TLP stored in the dedicated retry buffer in a sequence buffer. Upon receipt of a reset request for a VH, the link layer may purge the dedicated retry buffer associated with the VH. After purging, the multi-root device may send an ACK (acknowledge code) DLLP (data link layer packet), indicating that the VH has been successfully reset. By utilizing multiple retry buffers, the ACK DLLP response for a VH reset is sent as soon as the retry buffer pointers are reset to initial values.

Abstract: A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.

Abstract: An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of sum values by adding a plurality of pixel difference values between a current block and a reference block, one of the sum values corresponding to each of a plurality of smallest partitions of the current block. The second circuit configured to (i) generate a plurality of intermediate values from the sum values, one of the intermediate values corresponding to each of a plurality of possible partitions of the current block, (ii) store a plurality of lowest values among the intermediate values as the current block is moved through a search window and (iii) generate a motion signal conveying at least one motion vector based on the lowest values.

Abstract: A method for de-interlacing is disclosed. The method generally includes the steps of (A) determining a plurality of target mode values for a target pixel being synthesized to convert a current field into a current frame, wherein at least two of the target mode values are based on both (i) a plurality of original pixels and (ii) a plurality of synthesized pixels in a plurality of synthesized frames, (B) generating a plurality of candidate values for the target pixel using a plurality of interpolation techniques that includes a motion estimation interpolation utilizing a particular one of the synthesized frames and (C) selecting a particular one of the candidate values for the target pixel in response to the target mode values.

Abstract: A graphics rendering engine within a software development tool is used to perform software debug operations by analyzing the status of instructions within various stages of a superscalar processor pipeline. The debug operations are carried out using code breakpoints selected by a user through a graphical user interface. Once a line of code is selected, the processor pipeline can be examined by designating a highlighted color, for example, for certain stages and corresponding instructions that will proceed to the next stage, and not designating stages and corresponding instructions that will not proceed. This allows a user to visually examine the efficiency of the instruction throughput at select regions in the sequence of instruction addresses. Armed with the information, a user can then modify the sequence if desired.

Abstract: A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.

Abstract: Embodiments include methods and systems for processing XML documents. One embodiment is a system that includes a tokenizer configured to identify tokens in an XML document. A plurality of speculative processing modules are configured to receive the tokens and to at least partially process the XML document and to provide data indicative of the XML document. A first module is configured to perform further processing of the XML document using the data indicative of the XML document and configured to output the processed XML document. Each of the plurality of speculative processing modules is configured to asynchronously provide the data indicative of the XML document to the first module. Other embodiments include method and systems for performing the speculative processing.

Abstract: A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimensions for module may be determined. Region parameters may be adjusted prior to final placement and placement may be verified.

Abstract: Housings are described that include snap fittings or connections hat can be placed on portions of the housing to allow assembly of the housing in the field, without the need for assembly tools or welding. Reduced assembly time and cost, as well as the reduction/elimination of tooling costs for assembly tools and/or associated hardware can therefore be realized Exemplary embodiments of the present disclosure can include a snap fitting with first and second portions, e.g., male and female portions, including a portion having a tab or clip punched out of a sheet and including a holding protrusion or portion, and another portion having an aperture or depression configured and arranged to receive and be held by the holding portion. Preferred embodiments can be utilized as light pole base covers.

Abstract: Effective GDS-based channel length scaling. A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The poly lines and contacts can be shifted by starting at the center and going out radially, or by beginning at the perimeter and moving radially inward. The method can be used with any library cell design which is entirely GDS based, including, for example, 32 nm library cell design.

Abstract: An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.

Abstract: A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a lighting component and a mounting structure. The lighting component can include a light source, a plate, and a frame. The light source can include one or more lighting elements, such as light emitting diodes. The lighting component can be releasably secured to the mounting structure.

Abstract: A method for recovering errors on a multiple disk system. The method including the steps of (a) determining a location and type for one or more errors in a plurality of blocks on the multiple disk system, (B) determining a current error of the one or more errors that is closest to a start of the plurality of blocks, (C) recovering data for the current error using data read from drives other than the drive containing the current error and (D) determining whether any further errors are present on the drive that contained the current error.