Abstract: Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.

Abstract: An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to collect color statistics. The second circuit may be configured to sort colors based upon the color statistics collected by the first circuit. The third circuit may be configured to generate a mapping function between the sorted colors and a color space of a receiving standard.

Abstract: A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. Various types of data and fields may be provided into the user interface or data template. The location of relevant files, such as a cell or core netlist, may be provided within the template. Additionally, one or more modes may be selected by the user to define the manner in which the ETM file(s) are to be generated. An ETM file is automatically generated using the information provided in the data template.

Abstract: A method for decoding a bitstream is disclosed. The method generally comprises the steps of (A) generating a first signal and a second signal by parsing a common slice in the bitstream, (B) generating a third signal by entropy decoding the first signal, and (C) generating a video signal by combining the second signal and the third signal.

Abstract: Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.

Abstract: A system and method for remotely monitoring and controlling a data storage system comprising a web server that has an ability to send and receive communications with one or more data storage systems through the storage system's main data communication path or through an alternate path. The web server may include a routine which continuously monitors the status of the storage system as well as a routine which pushes changed data to a client device operating a browser. The system and method may consolidate the status and provide control of many different independent data storage systems simultaneously.

Abstract: The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.

Abstract: In one embodiment a control unit of a communication system exchanging a multiple-phase time-interleaved data includes a first Phase-Locked Loop (PLL) to generate a set of un-calibrated multiple-phase signals of a first-clock; a second-PLL, a pulse generator, a pulse-width measurement unit and a phase calibration engine to evaluate adjustments required in a temporal location of a logically critical voltage transition edge in each signal in the un-calibrated set; and a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the un-calibrated set to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the calibrated set includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: A switched preconditioner circuit is provided at the power input end of a light source to effectively drop the voltage of the light source to zero volts whenever the light source is required to be in an OFF state thereby eliminating the problem of unwanted current through the light source. The preconditioner circuit may include a terminal connected to a first power potential, a terminal connected to a power node at the power input end of the light source, and an input to receive a preconditioner control signal to place the preconditioner circuit in one of an ON state and an OFF state. The preconditioner circuit supplies the voltage to the power node in its ON state and effectively eliminates the voltage to the power node in its OFF state.

Abstract: An EMI shield apparatus for connecting to a CRU frame, a memory unit emitting EMI through a periphery of the CRU frame, the EMI shield apparatus comprising a shield base, a plurality of sides bordering the shield base for blocking EMI emitted from a portion of the periphery of the CRU frame, and a plurality of tabs connected to at least one of the plurality of sides for blocking EMI emitted from the corners of the periphery of the CRU frame when the plurality of sides are in a compressed condition.

Abstract: Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.

Abstract: A software-based RAID system is provided that enables configuration conflicts to be detected and resolved between a PD that is logically present but physically missing, and a PD that is physically and logically present. In accordance with the invention, a determination is made as to whether such a configuration conflict exists, and if so, the logically-present, but physically missing, reference identifier associated with the PD is remapped to a port number that currently is not in use.

Abstract: Embodiments of the invention include a method and apparatus for managing SAS zoning using initiator isolation. The method includes assigning initiator devices in the SAS domain to a first initiator zone group, assigning target devices in the SAS domain to a second target zone group, and establishing an access control policy in which each of the initiator devices assigned to the first initiator zone group can communicate with each of the target devices assigned to the second target zone group but no initiator devices assigned to the first initiator zone group can communicate with any other initiator devices assigned to the first initiator zone group. Assignment of devices can be based on attachment information associated with each device, such as the ZPSDS entry point of the device, the SAS address of the device, and the phy of the zoning expander device in the SAS domain that is closest to the device.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: A pseudo pipeline including a plurality of pseudo pipeline stages and a control circuit. The control circuit may be configured to control the plurality of pseudo pipeline stages to provide pseudo pipelined operation.

Abstract: A device and method for retrofitting a light fixture from use with a lamp socket that employs a conventional incandescent or metal halide lamp, to use with a light emitting diode (LED)-based lamp assembly. The lamp fixture has a collar with a base and an annular outer wall extending out from the base. The LED lamp device includes a neck base having an annular outer wall having a shaped outside surface that is placed into direct surface contact with the inner surface of the annular outer wall of the collar, to establish an effective heat-transferring interface. The shaped outer surface of the neck base provides proper fitting of the LED lamp device into the lighting fixture, and provides a heat-transferring interface over substantially all of the outer surface of the neck base, to dissipate heat away from the LED module. Aluminum material provides high thermal conductivity, light weight, availability, and low cost.

Abstract: Systems and devices are disclosed that can be aimed by external adjustment devices/features/means without the need to open the sealed LED module. Heat from the LEDs and/or LED mounting assembly can be transferred to the outside air while the module is tilted, e.g., up to 15 degrees, or more, from vertical. Additionally, the modular structure of the inground LED light can allow for upgrade/renewal of associated electronics with only minor disassembly. Moreover, the thermal dissipation/management afforded by the designs of embodiments can allow for an increase of the LED useful service life. The sealing of the inground light unit can preclude the chance of an end user (e.g., service technician) from causing the unit to leak and thereby cause premature failure.

Abstract: A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

Abstract: A method of trace optimization in a flattened netlist of a circuit is disclosed. The method generally includes the steps of (A) generating a first total result by tracing a first path through the flattened netlist, (B) writing an intermediate result in a memory, the intermediate result characterizing a module having a plurality of instances in the circuit, (C) adding the intermediate result as read from the memory to the first total result upon crossing each of the instances of the module along the first path and (D) writing the first total result into the memory.