Patents Assigned to Micronics
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Publication number: 20250183155Abstract: An example apparatus includes a plurality of signal wiring patterns, a plurality of shield patterns each provided between corresponding two of the signal wiring patterns, a common pattern coupled to each of the plurality of shield patterns, and a transistor coupled between the common pattern and a power line supplied with a fixed power potential.Type: ApplicationFiled: February 10, 2025Publication date: June 5, 2025Applicant: MICRON TECHNOLOGY, INC.Inventor: Tetsuji Takahashi
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Publication number: 20250182819Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.Type: ApplicationFiled: February 12, 2025Publication date: June 5, 2025Applicant: MICRON TECHNOLOGY, INC.Inventors: Tetsuya Arai, Shuichi Tsukada, Shun Nishimura, Yoshinori Matsui
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Publication number: 20250182823Abstract: An apparatus includes: a first memory mat; a second memory mat adjacent to the first memory mat; a peripheral circuit between the first memory mat and the second memory mat, the peripheral circuit defining a first boundary to the first memory mat and a second boundary to the second memory mat and including a plurality of wiring patterns in a wiring layer; and at least one dummy pattern in the wiring layer arranged on or along the first boundary.Type: ApplicationFiled: February 10, 2025Publication date: June 5, 2025Applicant: MICRON TECHNOLOGY, INC.Inventor: Harutaka Honda
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Publication number: 20250185248Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.Type: ApplicationFiled: February 3, 2025Publication date: June 5, 2025Applicant: Micron Technology, Inc.Inventors: John D. Hopkins, David Daycock
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Patent number: 12324143Abstract: Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 17, 2020Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Ke-Hung Chen, Christopher W. Petz, Pankaj Sharma, Yong Mo Yang
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Patent number: 12321274Abstract: System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.Type: GrantFiled: February 29, 2024Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Dean E. Walker, Tony M. Brewer
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Patent number: 12321228Abstract: A plurality of signals within a memory sub-system are analyzed by a signal analyzer component. Relevant signals among the plurality of signals are determined by the signal analyzer component such that the relevant signals comprise a subset of signals among the plurality of signals. Information corresponding to the relevant signals is sampled by the signal analyzer component and the signal analyzer component is responsible for extracting the information corresponding to the relevant signals among the plurality of signals.Type: GrantFiled: April 4, 2024Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventor: Shawn Storm
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Patent number: 12321288Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.Type: GrantFiled: August 30, 2022Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Hyun Yoo Lee, Kang-Yong Kim, Jason McBride Brown, Venkatraghavan Bringivijayaraghavan, Vijayakrishna J. Vankayala
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Patent number: 12324157Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.Type: GrantFiled: March 27, 2023Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Jivaan Kishore Jhothiraman, John Mark Meldrim
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Patent number: 12324244Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.Type: GrantFiled: September 2, 2021Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Glen H. Walters, John A. Smythe, III, Scott E. Sills, John F. Kaeding
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Patent number: 12321229Abstract: Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.Type: GrantFiled: January 17, 2024Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Joseph M. McCrate, Kirthi Shenoy, Marco Sforzin, Brian M. Twait
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Patent number: 12321266Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.Type: GrantFiled: February 29, 2024Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Xiangyu Tang, David Ebsen, Ying Huang, Sundararajan Sankaranarayanan
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Patent number: 12323336Abstract: A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.Type: GrantFiled: May 3, 2022Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventors: Tony Brewer, David Patrick
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Patent number: 12322585Abstract: The present disclosure includes apparatuses and methods related to sublimation in forming a semiconductor. In an example, a method may include forming a sacrificial material in an opening of a structure, wherein the sacrificial material displaces a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to sub-atmospheric pressure.Type: GrantFiled: March 25, 2021Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventor: Matthew S. Thorum
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Patent number: 12321286Abstract: A one-time programmable (OTP) memory is included in both a memory device and a processing device. The OTP memories store encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.Type: GrantFiled: August 11, 2023Date of Patent: June 3, 2025Assignee: Micron Technology, Inc.Inventor: Gil Golov
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Publication number: 20250173255Abstract: Apparatuses and methods for controller signaling of refresh operations. A memory may receive a first or a second type of refresh command. Responsive to the first type of refresh command a first type of refresh operation (e.g., a sequential refresh operation) may be performed. Responsive to the second type of refresh operation a second type of refresh operation (e.g., a targeted refresh operation) may be performed.Type: ApplicationFiled: July 16, 2024Publication date: May 29, 2025Applicant: Micron Technology, Inc.Inventor: Randall J. Rooney
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Publication number: 20250174619Abstract: Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.Type: ApplicationFiled: January 29, 2025Publication date: May 29, 2025Applicant: Micron Technology, Inc.Inventor: Werner Juengling
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Patent number: 12314181Abstract: A computing device having a computer express link (CXL) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. The memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. One or more storage access queues can be configured in the memory device. The host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. Optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.Type: GrantFiled: February 5, 2024Date of Patent: May 27, 2025Assignee: Micron Technology, Inc.Inventor: Luca Bert
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Patent number: 12313885Abstract: A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of formation. The coupling structure is sloped relative to a horizontal surface of the photonic structure such that light entering or leaving the photonic structure is substantially normal to its upper surface.Type: GrantFiled: June 16, 2023Date of Patent: May 27, 2025Assignee: Micron Technology, Inc.Inventor: Harel Frish
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Patent number: 12314166Abstract: Methods, systems, and devices for mapping descriptors for read operations are described. A memory device may include a first cache may include a mapping table between the logical addresses and the physical addresses, and a second cache may include one or more descriptors of one or more physical addresses of the memory array. A descriptor may include a starting logical address, a starting physical address, and a quantity of addresses in the descriptor, and may be configured to identify addresses or sets of address that are frequently accessed. When an access command (e.g., a read command) is received, the first cache may be queried and then the second cache may be queried (if there is a cache miss at the first cache). The physical address of the data of the memory array may be determined (and accessed) based on the descriptors stored in the second cache.Type: GrantFiled: March 12, 2024Date of Patent: May 27, 2025Assignee: Micron Technology, Inc.Inventor: Xing Hui Duan