Patents Assigned to Micronics
  • Patent number: 12315813
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through a lowest of the conductive tiers. The TAV constructions individually comprise an insulative lining having a lowest surface that is directly against metal material in the lowest conductive tier. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Jordan D. Greenlee, John D. Hopkins
  • Patent number: 12314590
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Tomer Eliash
  • Patent number: 12316640
    Abstract: In some implementations, a device of an Internet of Things (IoT) network may receive, from a host associated with the IoT network, information associated with the IoT network. The device may store, via a memory controller of the device, the information in a memory with an embedded hardware security module of the device, wherein the device serves as a root of trust for the host using the information stored in the memory. The device may receive, from the host, a request to perform a security function. The device may perform, based on the request, the security function using the information stored in the memory. The device may generate an alert based on an outcome of the security function. Numerous other implementations are described.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Sourin Sarkar, Kanika Mittal, Gowrishankar Gajendiran
  • Patent number: 12314573
    Abstract: Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Steffen Buch, Marco Redaelli
  • Patent number: 12315574
    Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, determining whether the read operation has failed, in response to determining that the read operation has failed, obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, determining whether to initiate auto-calibrated corrective read, in response to determining to initiate auto-calibrated corrective read, performing read level offset calibration to determine a set of calibrated read level offsets, and causing the set of target cells to be read using the set of calibrated read level offsets.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Chengbin Sun, Carmine Miccoli, Violante Moschiano, Srinath Venkatesan, Walter Di Francesco
  • Patent number: 12314386
    Abstract: In some implementations, a system includes a set of servers configured to establish a set of virtual machines to provide a computing environment; a set of compute express link (CXL) interface components configured to communicate with the set of servers via a set of CXL interconnects; and a controller configured to at least one of: encrypt protocol data against a CXL interposer security threat associated with the set of CXL interconnects or a malicious extension security threat, provide a secure handshake verification of an identity of the set of CXL interface components, enforce a chain of trust rooted in hardware of the set of CXL interface components; restrict access to an area of memory of the set of CXL interface components that stores security data for verified or secured processes; or perform a security check and set up a set of security features of the set of CXL interface components.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Orlando, Niccolò Izzo, Federica Cresci, Angelo Alberto Rovelli, Craig A Jones, Danilo Caraccio, Luca Castellazzi
  • Patent number: 12314177
    Abstract: A total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. Respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. It is determined that the total count for the address mapping table satisfies a threshold criterion. A first section of the plurality of sections with a highest section count is identified based on the respective section counts. The first section of the address mapping table is written to a non-volatile memory device.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Byron Harris, Daniel Boals, Abedon Madril
  • Patent number: 12315833
    Abstract: Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Wei Zhou
  • Publication number: 20250167811
    Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Jaime Cummins
  • Publication number: 20250166722
    Abstract: Systems might include tester hardware for connection to a die containing a memory comprising a plurality of groupings of memory cells and a predictive model in communication with the tester hardware, wherein a controller of the tester hardware is configured to generate characterization data corresponding to a first grouping of memory cells, wherein the predictive model is configured to generate an indication of expected endurance for the first grouping of memory cells in response to the characterization data in response to process data corresponding to the first grouping of memory cells, and wherein the controller is further configured to store a value to the memory indicative of the indication of expected endurance. Methods could use the predictive model in wear leveling within a memory, and memories could use information regarding expected endurance in wear leveling.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 22, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Mohammed A. Khan
  • Publication number: 20250166673
    Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Manami SENOO, Hidekazu NOGUCHI, Yoshio MIZUKANE
  • Publication number: 20250169072
    Abstract: Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 22, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Gordon A. Haller, William R. Kueber, Zachary D. Beaman, Christopher G. Shea, Taehyun Kim
  • Publication number: 20250166704
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins, Collin Howder, Jordan D. Greenlee
  • Publication number: 20250159889
    Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Damir Fazil, Michael E. Koltonski
  • Publication number: 20250156923
    Abstract: A size comparison system may generate a size comparison by determining a size of an item based on extracted size data corresponding to the item. A comparison item is selected and the size comparison is generated between the item and the comparison item based on the size of the item. A visual rendering of the item and the comparison item is generated based on the size comparison and is displayed to a user.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 15, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Carla L. Christensen, Bethany M. Grentz, Xiao Li, Sumana Adusumilli, Libo Wang
  • Publication number: 20250157526
    Abstract: An example apparatus includes a first circuit configured to receive a plurality of first write data and then a plurality of second write data responsive to a write command; a second circuit configured to select one or ones of the plurality of first write data and one or ones of the plurality of second write data based, at least in part, on a first selection signal and a second selection signal following the first selection signal, respectively; and a third circuit configured to: receive an internal write command signal provided correspondingly to the write command; mask a portion of the internal write command signal a timing of which partially overlaps the plurality of first write data to provide a masked internal write command signal; and provide the second selection signal based, at least in part, on the second internal command signal.
    Type: Application
    Filed: July 22, 2024
    Publication date: May 15, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yuichiro Sato, Shingo Mitsubori, Ryo Fujimaki
  • Publication number: 20250157537
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Shyam Surthi, Matthew Thorum
  • Publication number: 20250156087
    Abstract: Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20250159945
    Abstract: Some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. The charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the stack. Charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. The charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.
    Type: Application
    Filed: January 14, 2025
    Publication date: May 15, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Manzar Siddik, Terry H. Kim
  • Publication number: 20250159875
    Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Luan C. Tran, Guangyu Huang, Haitao Liu