Patents Assigned to Micronics
  • Patent number: 12301711
    Abstract: A request for password generation is received from a host system. In response to receiving the request, a password derivation key is generated based on a key derivation seed. A password is derived from the password derivation key, and a wrapping key is derived from the password. The wrapping key is used to wrap an authorization state indication, which is stored in local memory. Encrypted data is generated based on an encryption of the key derivation seed using an asymmetric encryption key. The encrypted data is provided in response to the request.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: James Ruane, Robert W. Strong
  • Patent number: 12299282
    Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.
    Type: Grant
    Filed: May 28, 2024
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Vinay Vijendra Kumar Lakshmi, Vijaya Janarthanam
  • Patent number: 12299315
    Abstract: Methods, systems, and devices for coding for quad-level memory cells having a replacement gate configuration are described. Data may be received for storage in a memory device that includes a memory array with memory cells having a replacement gate configuration. The data may be assigned to a plurality of different types of pages within a memory cell of the memory cells using a unit-distance code. The data may be written to the plurality of pages of the different types within the memory cell based at least in part on assigning the data to the plurality of pages of the different types within the memory cell using the unit-distance code to distribute the pages in a way to avoid inconsistent voltage shifting across the plurality of pages of different types.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Curtis Egan
  • Patent number: 12299326
    Abstract: Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which the request is directed is determined. A command is sent to the memory for the operation. A request is sent to the memory for a status of the command based upon the determined command completion time.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 13, 2025
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Karl D. Schuh, Daniel J. Hubbard
  • Patent number: 12300736
    Abstract: Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 12300765
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Patent number: 12300300
    Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: John Christopher Sancon, Yang Lu, Kang-Yong Kim, Mark Kalei Hadrick, Hyun Yoo Lee
  • Patent number: 12300322
    Abstract: A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Vinh Quang Diep, Jeffrey Ming-Hung Tsai, Ching-Huang Lu, Yingda Dong
  • Patent number: 12300339
    Abstract: A system includes a memory component and a processing device operatively coupled with the memory component. The processing device performs a test of the memory component by generating an error correction code (ECC) value for an initial operation of the test based on an address in the memory component on which the initial operation of the test is performed, generating ECC values for subsequent operations of the test, and reporting the ECC value generated for the last of the subsequent operations of the test in an event log. The ECC value for each respective subsequent operation of the test is generated based on an address in the memory component on which that respective subsequent operation of the test is performed, and the ECC value generated for the operation of the test that was performed immediately before that respective subsequent operation.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kok Hua Tan, Chee Hock Ngo, Michael T. Brady
  • Patent number: 12298835
    Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Roya Baghi, Erica M. Gove, Zahra Hosseinimakarem, Cheryl M. O'Donnell
  • Patent number: 12300318
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Jordan D. Greenlee, John D. Hopkins
  • Patent number: 12300321
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether one or more memory access operations performed on a range of consecutive wordlines of a memory device satisfy one or more criteria. The operations further include, responsive to determining that the one or more memory access operations satisfy the one or more criteria, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines of the memory device.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
  • Patent number: 12301713
    Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.
    Type: Grant
    Filed: June 14, 2024
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 12299280
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 12299318
    Abstract: A set of data items programmed to a first region of a memory subsystem is identified. The set of data items is programmed to the first region according to an initial sequence. A determination is made of whether the initial sequence corresponds to a target sequence associated with accessing the set of data items. Responsive to a determination that the initial sequence does not correspond to the target sequence, the set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: May 13, 2025
    Assignee: Micron Technolgy, Inc.
    Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
  • Patent number: 12299325
    Abstract: Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Aaron P. Boehm, Todd Jackson Plum, Scott D. Van De Graaff, Scott E. Schaefer, Mark D. Ingram
  • Patent number: 12300298
    Abstract: Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Giorgio Servalli, Angelo Visconti, Marcello Mariani, Alessandro Calderoni
  • Patent number: 12300316
    Abstract: Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Umberto di Vincenzo, Ferdinando Bedeschi, Michele Maria Venturini, Claudia Palattella
  • Patent number: 12300351
    Abstract: Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Kang-Yong Kim
  • Patent number: 12298838
    Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki