Patents Assigned to Micronics
  • Patent number: 12293790
    Abstract: Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Yoshihiko Kamata, Akira Goda
  • Patent number: 12292831
    Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.
    Type: Grant
    Filed: March 26, 2024
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, David Aaron Palmer
  • Patent number: 12292843
    Abstract: Systems, apparatuses, and methods related to transferring data to a memory device based on importance are described. A memory apparatus includes a first memory device, a second memory device having a lower write latency than the first memory device, and a controller coupled to the first memory device and second memory device via a compute express link (CXL) interface. The controller is configured to assign an importance level to a write request based on data associated with the write request, a hierarchy of importance levels for different data types, and the second memory device having a lower write latency than the first memory device. The controller is further configured to transfer the data to the first memory device in response to the assigned importance level having a first value and transfer the data to the second memory device in response to the assigned importance level having a second value.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Robert Bielby, Junichi Sato
  • Patent number: 12295147
    Abstract: Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Robustelli, Innocenzo Tortorelli
  • Patent number: 12295140
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Allen McTeer, Rita J. Klein, John D. Hopkins, Nancy M. Lomeli, Xiao Li, Alyssa N. Scarbrough, Jiewei Chen, Naiming Liu, Shuangqiang Luo, Silvia Borsari, John Mark Meldrim, Shen Hu
  • Patent number: 12293789
    Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Mattia Boniardi, Mattia Robustelli
  • Patent number: 12293992
    Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Chin Hui Chong, Hong Wan Ng
  • Patent number: 12293101
    Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.
    Type: Grant
    Filed: January 25, 2024
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
  • Patent number: 12292794
    Abstract: Methods, systems, and devices for techniques for managing memory exception handling are described. A memory device may write first data associated with a first access command to a first portion of a buffer of a memory device. The memory device may determine a programming failure to write second data to a page of a first block of the memory device. In response to determining the programming failure, the memory device may perform an access operation associated with the first access command to vacate the first data from the first portion of the buffer. In response, the memory device may write the second data to the first portion of the buffer. The memory device may write the second data from the first portion of the buffer to a page of a second block of the memory device in response to writing the second data to the first portion of the buffer.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Santhosh Kumar Siripragada
  • Patent number: 12293783
    Abstract: Systems and methods related to a memory device that includes a command interface configured to receive read commands and write commands to invoke read and write operations. The memory device also includes a memory bank having multiple memory cells implemented using ferroelectric layers between plate lines and digit lines. The memory device also includes bank control circuitry configured to control operation of the memory bank. The operation of the memory bank includes programming both high and low logic values as a write back to the multiple memory cells during a read and write phase where the read and write operations are performed after sensing values from the multiple memory cells.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Giovanni Mazzeo
  • Patent number: 12293795
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Robert W. Mason, Scott Anthony Stoller, Pitamber Shukla, Ekamdeep Singh
  • Publication number: 20250140303
    Abstract: An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.
    Type: Application
    Filed: June 24, 2024
    Publication date: May 1, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Honoka Enomoto, Takashi Tomatsu, Masaru Morohashi, Hideo Shimizu
  • Publication number: 20250142820
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Publication number: 20250142875
    Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Hong Li, Erica L. Poelstra
  • Publication number: 20250140324
    Abstract: Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
  • Publication number: 20250140306
    Abstract: Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Christopher G. Wieduwilt, John P. Behrend
  • Publication number: 20250140304
    Abstract: A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.
    Type: Application
    Filed: July 16, 2024
    Publication date: May 1, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Yukimi Morimoto, Takayuki Miyamoto, Atsuko Momma
  • Publication number: 20250140298
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20250142827
    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 1, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
  • Patent number: 12288585
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 29, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, John D. Hopkins, Purnima Narayanan, Vinayak Shamanna, Justin D. Shepherdson