Abstract: A machine learning model may be trained to denoise an image. The machine learning model may identify noise in an image of a sequence based at least in part, on at least one other image of the sequence. The machine learning model may include a recurrent neural network. The machine learning model may have a modular architecture including one or more building units. The machine learning model may have a multi-branch architecture. The noise may be identified and removed from the image by an iterative process.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

Abstract: Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: Apparatuses, machine-readable media, and methods related to vehicle diagnosis and repair are described. Receiving vehicle status information from a control panel and/or on board diagnostic (OBD) unit of a vehicle at a vehicle diagnosis and repair too can provide valuable information to an owner and/or user of a vehicle. Computing devices (e.g., mobile devices and/or modules having a computing device) can be configured to run an application (e.g., a vehicle diagnosis and repair tool) to determine whether a vehicle needs to be repaired or serviced according to examples of the present disclosure. The vehicle diagnosis and repair tool can receive vehicle status information, determine the repairs and/or service that the vehicle needs, and initiate the vehicle repairs and/or service.

Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Abstract: Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers in the hierarchical structure can be provided as inputs to higher layers. In this manner, lower layers can perform a lower level of analysis (e.g., more basic/fundamental analysis), while a higher layer can perform a higher level of analysis (e.g., more complex analysis) using the outputs from one or more lower layers. In an example, the hierarchical structure performs pattern recognition.

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Abstract: Apparatuses and methods can be related to encoding traffic between a host and a deep learning accelerator (DLA). Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.

Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

Abstract: A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

Abstract: A controller performs an access operation on a word line which is in a portion of a memory array in a memory device. The controller counts accesses on a portion-by-portion basis (e.g., a bank-by-bank basis, a sub-bank-by-sub-bank basis, etc.). The memory counts accesses on a word line-by-word line basis. The memory sets a refresh management (RFM) flag for a portion based on the counts associated with the word lines in that portion. The controller checks the RFM flag for a portion based on the access count for the portion. The controller issues an RFM command after checking the RFM flag if the RFM flag is set.

Abstract: An example apparatus includes a data bus including a first portion having a timing domain which is controlled based on a first timing signal and further including a second portion having a timing domain which is controlled based on a second timing signal, and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver. The timing control circuit includes a variable delay to add an amount of delay to a first control signal to generate a second control signal. The data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus responsive to the second control signal.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.