Abstract: Embodiments of the disclosure provide an apparatus comprising: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to gate nodes of the load transistors; and first and second capacitive devices. Gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. The first input transistor and the first load transistor are coupled to a first output. The second input transistor and the second load transistor are coupled to a second output. The gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. The first and second capacitive devices are coupled to the first and second inputs and to the gate nodes of the first and second load transistors, respectively.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: The present disclosure is related to an imaging camera including a filter wheel. The filter wheel includes a main body including a plurality of receptacles and a plurality of wedges. Each of the wedges is attached to one of the plurality of receptacles. Each of the wedges includes a receiving orifice to a filter. The main body of the filter wheel includes an adapter configured to receive an actuator to actuate the filter wheel. Each wedge is removably attached to one of the plurality of receptacles. The filter wheel is configured to rotate around a central axis of the main body.

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

Abstract: A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

Abstract: Methods, systems, and apparatuses related to autonomous vehicle object detection are described. An autonomous vehicle can capture an image corresponding to an unknown object disposed within a sight line of the autonomous vehicle. Processing resources available to a plurality of memory devices associated with the autonomous vehicle can be reallocated in response to capturing the image and an operation involving the image corresponding to the unknown object to classify the unknown object can be performed using the reallocated processing resources.

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. Charge-storage-material-segments are adjacent to the conductive levels of the stack, and are between the channel material and the conductive levels. The charge-storage-material-segments contain one or more high-k oxides. At least a portion of each of the charge-storage-material-segments is vertically wider than the conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.

Abstract: In some aspects, the techniques described herein relate to a device including: a processor; and a storage medium for tangibly storing thereon logic for execution by the processor, the logic including instructions for: storing a group digital certificate, the group digital certificate including a plurality of unique identifier (UID) values and a plurality of corresponding public keys; receiving onboarding data and a digital signature from a client device, the onboarding data including a UID of the client device and a public key of the client device and the digital signature generated using the onboarding data and a private key corresponding to the public key; validating the digital signature using the public key; confirming that the UID matches at least one UID in the group digital certificate; and onboarding the client device.

Abstract: Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.

Abstract: Methods, systems, and apparatuses related to autonomous vehicle object detection are described. A method can include receiving, by an autonomous vehicle, an indication that the autonomous vehicle has entered a network coverage zone generated by a base station and performing an operation to reallocate computing resources between a plurality of different types of memory devices associated with the autonomous vehicle in response to receiving the indication. The method can further include capturing, by the autonomous vehicle, data corresponding to an unknown object disposed within a sight line of the autonomous vehicle and performing, using the reallocated computing resources, an operation involving the data corresponding to the unknown object to classify the unknown object.

Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include an array of memory cells and a transistor located on a periphery of the array of memory cells. A number of data lines are shown coupled to memory cells in the array, wherein the number of data lines extend over a first metal gate of a transistor in the periphery of the array, where the number of data lines are formed from a second metal, and form a direct interface with the first metal gate.

Abstract: In some examples, a machine learning model may be trained to denoise an image. In some examples, the machine learning model may identify noise in an image of a sequence based at least in part, on at least one other image of the sequence. In some examples, the machine learning model may include a recurrent neural network. In some examples, the machine learning model may have a modular architecture including one or more building units. In some examples, the machine learning model may have a multi-branch architecture. In some examples, the noise may be identified and removed from the image by an iterative process.