Patents Assigned to Micronics
  • Patent number: 12274051
    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include an array of memory cells and a transistor located on a periphery of the array of memory cells. A number of data lines are shown coupled to memory cells in the array, wherein the number of data lines extend over a first metal gate of a transistor in the periphery of the array, where the number of data lines are formed from a second metal, and form a direct interface with the first metal gate.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hyucksoo Yang, Jongpyo Kim, Byung Yoon Kim
  • Patent number: 12272030
    Abstract: In some examples, a machine learning model may be trained to denoise an image. In some examples, the machine learning model may identify noise in an image of a sequence based at least in part, on at least one other image of the sequence. In some examples, the machine learning model may include a recurrent neural network. In some examples, the machine learning model may have a modular architecture including one or more building units. In some examples, the machine learning model may have a multi-branch architecture. In some examples, the noise may be identified and removed from the image by an iterative process.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Bambi L DeLaRosa, Katya Giannios, Abhishek Chaurasia
  • Patent number: 12272421
    Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Jiewei Chen, Mithun Kumar Ramasahayam, Tomoko Ogura Iwasaki
  • Patent number: 12274057
    Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 12271592
    Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard
  • Patent number: 12272164
    Abstract: A method for performing automated GUI-driven OpROM validation starts with a processor executing an automated test script; and in response to executing the automated test script, the processor is caused to remotely accessing a memory sub-system using a web driver and an interface. The processor causes a BIOS terminal window of the memory sub-system to be displayed on a display screen. The processor captures a screenshot of the BIOS terminal window and generating an image based on the screenshot. The processor converts the image to text using OCR and generates an output comprising BIOS configuration details based on the text using a machine-learning algorithm. The processor then analyzes the output to validate the memory sub-system when no errors are detected in the output or to flag the memory sub-system when errors are detected in the output. Other embodiments are described herein.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Shiva Pahwa, Harsha Vardhana Gonchigara Vemanna, Sathyashankara Bhat Muguli
  • Patent number: 12271618
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to identify a center of valley (CoV) of a set of read levels. The controller detects a read error associated with reading data from the set of memory components in accordance with an individual read level of a plurality of read levels and, in response to detecting the read error, generates a plurality of bins as a function of a plurality of check failure bit count values and one or more error count values corresponding to a set of read levels adjacent to the individual read level. The controller computes the CoV for the individual read level based on a pair of read levels defined by a set of the plurality of bins and updates a read level used to read the data based on the computed CoV.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: April 8, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Kyungjin Kim
  • Publication number: 20250110830
    Abstract: Apparatuses, systems, and methods for alternate memory die metadata storage. A memory module includes a number of memory devices. A controller writes data and metadata to the module. The data is stored in the memory devices, while the metadata is stored in a selected portion of the memory devices. The selected portion of the memory devices may use separate write enable signals to protect bit lines which the metadata is not being written to.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20250111887
    Abstract: Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20250111045
    Abstract: Memory devices direct refresh management (DRFM) attack identification. A DRFM logic circuit receives DRFM aggressor address and compares it to a previous DRFM aggressor address. If there is not a match, then a DRFM operation is performed. If there is a match, then the DRFM operation may be skipped. This may prevent repeated DRFM operations from being performed on a same DRFM aggressor address.
    Type: Application
    Filed: June 18, 2024
    Publication date: April 3, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Yunyoung Lee, Yuan He
  • Publication number: 20250112086
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • Publication number: 20250111872
    Abstract: Apparatuses, systems, and methods for refresh rate register adjustment based on a targeted refresh queue. A memory includes a temperature sensor which measures a temperature of the memory. The memory also includes a targeted refresh queue which stores identified aggressor addresses. A value of a refresh rate register is set based on both the measured temperature and the number of addresses in the queue. A controller of the memory reads the value of the refresh rate register and provides a refresh signal with timing based on the refresh rate register. In some embodiments, a ratio of targeted and normal refresh operations is adjusted based on how many addresses are in the targeted refresh queue.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Wonjun Choi, Hyun Yoo Lee
  • Publication number: 20250112643
    Abstract: Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20250110643
    Abstract: Apparatuses, systems, and methods for bounded fault compliant metadata storage. A memory module may be capable of repairing information along a portion of the data terminals of a memory device. To prevent errors in the metadata from propagating across more than the correctable portion, the metadata may be provided along a portion of the data terminals, while the data associated with that metadata is provided along more data terminals. For example, in a 9×2p2 module the data may use two terminals, while the metadata only uses one. In a 5×2p4 module, the metadata may use a pair of terminals, while the data uses four.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20250113487
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, M. Jared Barclay, Bhavesh Bhartia, Chet E. Carter, John D. Hopkins, Andrew Li, Haoyu Li, Alyssa N. Scarbrough, Grady S. Waldo
  • Publication number: 20250110825
    Abstract: Apparatuses, systems, and methods for read/modify/write single-pass metadata access operations. During a write a memory receives data bits and at least one metadata bit and a column address which includes column select bits and column sub-select bits. A column decoder selects a set of bit lines in an extra column plane based on the column select bits and a set of bits is read out. A subset of that set of bits is selected based on the column sub-select bits and overwritten with the at least one metadata bit. The modified set of bits is written back to the extra column plane.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 12267424
    Abstract: The disclosed embodiments are directed to preventing the writing of malformed cryptographic keys to a memory device. In one embodiment, a system is disclosed comprising a storage array, the storage array storing a first cryptographic key; and a processor configured to: receive a command from a host processor, the command including a second cryptographic key, a first signature, a second signature, and at least one field, determine that the first signature is valid using the second cryptographic key and the at least one field, determine that the second signature is valid using the first cryptographic key, the first signature and the at least one field, and replace the first cryptographic key with the second cryptographic key after determining that both the first signature and second signature are valid.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Zhan Liu
  • Patent number: 12265710
    Abstract: Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Xing Wang, Zhen Gu, Xu Zhang, Liping Xu
  • Patent number: 12265447
    Abstract: An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen, Violante Moschiano
  • Patent number: 12266647
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer