Patents Assigned to Micronics
  • Patent number: 12260098
    Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Yu-Sheng Hsu, Kang-Yong Kim, Ke Wei Chan
  • Patent number: 12260896
    Abstract: Methods, apparatuses, and systems related to operations for memory process feedback. A controller can monitor memory activities, such as processes, identify row hammer aggressors, and perform mitigating steps to the row hammer aggressors. The controller may have a table of addresses of row hammer aggressors and perform operations of tracking row hammer aggressors. The controller can determine whether the number of aggressors reaches a threshold. When the number of aggressors reaches the threshold, the controller can send a message with the aggressor addresses to the operating system. The operating system can perform mitigating steps to the row hammer aggressors. In some embodiments, the controller may identify the row hammer aggressors and inject poisoned data into the process to mitigate the row hammer aggressors.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 12259812
    Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Brian Toronyi
  • Patent number: 12260101
    Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tom V. Geukens, Byron D. Harris
  • Patent number: 12260908
    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
  • Patent number: 12260115
    Abstract: Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.
    Type: Grant
    Filed: January 25, 2024
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Olivier Duval, Christopher Joseph Bueb
  • Patent number: 12261810
    Abstract: Methods, systems, and devices for communications are described. A connection may be established between a remote device that includes an imaging device and a device. Based on establishing the connection, first visual data associated with the imaging device may be received at the device. A second connection between the device and a communication device may be established, where communications between the device and the communication device may be supported via an application running at the device. Based on establishing the second connection, the visual data may be transmitted from the mobile device to the communication device via the application.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Zoltan Szubbocsev
  • Patent number: 12259781
    Abstract: A method includes: generating, based on a hash function using at least one input including first data, a first digest; storing the first data in a memory; reading the first data from the memory; generating, based on the read data, a second digest; comparing the first digest and the second digest; and determining, based on comparing the first digest and the second digest, whether the read data is corrupted.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 12260110
    Abstract: Disclosed is a system comprising a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs). The operations performed by the processing device further include receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that a data structure associated with the group of memory cells references a second range of LBAs, blocking the memory access command; responsive to determining that the first range of LBAs does not include each LBA of the second range of LBAs, performing, on the group of memory cells, a trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yueh-Hung Chen, Fangfang Zhu, Horia Simionescu, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 12260916
    Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
  • Patent number: 12260931
    Abstract: A method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paul Philip Grahek, Jacob Walter Rice
  • Patent number: 12259257
    Abstract: Methods and apparatuses associated with updating a map using images are described. An apparatus can include a processing resource and a memory resource having instructions executable to a processing resource to monitor a map including a plurality of locations, receive, at the processing resource, the memory resource, or both, and from a first source, image data associated with a first location, identify the image data as being associated with a missing portion, an outdated portion, or both, of the map, and update the missing portion, the outdated portion, or both, of the map with the image data.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Kathryn H. Russo, Aparna U. Limaye, Gurtaranjit Kaur
  • Patent number: 12260097
    Abstract: In some implementations, a memory device may determine, from a list of key-value pair sets, a key-value pair set. The memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a first key that is included in at least one other key-value pair set from the list of key-value pair sets. The memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a second key that is not included in at least one other key-value pair set from the list of key-value pair sets. The memory device may form a new key-value pair set that excludes the first key and includes the second key. The memory device may replace the key-value pair set selected from the list of key-value pair sets with the new key-value pair set.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Gregory Alan Becker, Alexander Tomlinson
  • Patent number: 12261613
    Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.
    Type: Grant
    Filed: March 18, 2024
    Date of Patent: March 25, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Vijayakrishna J. Vankayala
  • Publication number: 20250096042
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Indra V. Chary
  • Publication number: 20250095713
    Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William C. Waldrop, Liang Chen, Shingo Mitsubori, Ryo Fujimaki, Atsuko Momma
  • Publication number: 20250098228
    Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi
  • Publication number: 20250094278
    Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.
    Type: Application
    Filed: July 19, 2024
    Publication date: March 20, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Marco SFORZIN, Emanuele CONFALONIERI, Daniele BALLUCHI, Danilo CARACCIO, Nicola DEL GATTO, Rishabh DUBEY
  • Publication number: 20250094262
    Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.
    Type: Application
    Filed: July 29, 2024
    Publication date: March 20, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Victor Wong, Donald Morgan
  • Patent number: D1068072
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: March 25, 2025
    Assignee: Phoenix-Micron, Inc.
    Inventor: Jonathan Roy Thorn