Patents Assigned to Micronics
  • Patent number: 12242884
    Abstract: Various examples are directed to systems and methods for performing operations in a reconfigurable compute fabric. A dispatch interface may send a first asynchronous message to a first flow controller of a first synchronous flow. The first asynchronous message may instruct the first flow controller to begin execution of a first-level loop. The first synchronous flow may send a second asynchronous message to a second flow controller of a second synchronous flow. The second asynchronous message may instruct the second flow controller to execute a second-level loop. The first flow controller may receive a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Douglas Vanesko, Bryan Hornung
  • Patent number: 12241621
    Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 12245426
    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Lifang Xu, Jordan D. Greenlee
  • Patent number: 12243600
    Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yoav Weinberg, Evgeni Bassin
  • Patent number: 12243607
    Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Schaefer
  • Patent number: 12243617
    Abstract: Devices and methods for operating a low-power memory device includes a first data input (DQ) circuitry including an input buffer configured to generate a loopback data signal based at least in part on a data signal received at the first DQ circuitry when the low-power memory device operates in a feedback mode. A second DQ circuitry includes an output buffer configured to receive the loopback data signal from the first DQ circuitry and to output the loopback data signal via a data pin.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Yoshihito Morishita
  • Patent number: 12244324
    Abstract: A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Di Hsien Ngu
  • Patent number: 12242745
    Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Binbin Huo
  • Patent number: 12242755
    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Murong Lang, Ching-Huang Lu, Nagendra Prasad Ganesh Rao
  • Patent number: 12242343
    Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Melissa I. Uribe, Aaron P. Boehm, Scott E. Schaefer, Steffen Buch
  • Patent number: 12243579
    Abstract: Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yuko Watanabe, Takefumi Shirako
  • Patent number: 12242385
    Abstract: Methods, systems, and devices for virtual addresses for a memory system are described. In some examples, a virtual address space may be shared across a plurality of memory devices that are included in one or more domains. The memory devices may be able to communicate with each other directly. For example, a first memory device may be configured to generate a data packet that includes an identifier and an address that is included in the shared virtual address space. The data packet may be transmitted to a second memory device based on the identifier, and the second memory device may access a physical address based on the address.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Bryan Hornung, Tony M. Brewer
  • Patent number: 12242734
    Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Guang Hu, Ting Luo
  • Patent number: 12244316
    Abstract: An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 12242726
    Abstract: Methods, systems, and devices for capability messaging for memory operations across banks with multiple page access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device. Techniques are further described for the generation and performance of internal access commands in accordance with a data transfer type indicated by a host system.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet V. Ayyapureddi
  • Patent number: 12242346
    Abstract: Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Fatma Arzum Simsek-Ege
  • Patent number: 12243807
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 12242722
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tomer Eliash, Sead Zildzic, Jr.
  • Patent number: 12242390
    Abstract: Methods, apparatuses, and systems related to securing memory data are described. A hardware circuit is configured to encrypt and decrypt memory data using a scrambling key unique to a computing process processing the memory data. In writing the memory data, the hardware circuit generates scrambled memory data based on encrypting the memory data according to the security key. The scrambled memory data is stored for the write operation instead of the memory data. When the same process reads back the scrambled data, the same security key can be used to decrypt the scrambled data and recover the initial unscrambled memory data.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Brett K. Dodds
  • Patent number: 12243801
    Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Xiaopeng Qu, Chan H. Yoo