Patents Assigned to NEC Electronics
  • Patent number: 7830336
    Abstract: An output buffer circuit constituted by a totem-pole circuit where two NchMOS transistors are cascade-connected, and the connection point of the two MOS transistors are connected to a data electrode of a display cell, improves the power recovery rate of a driver device of a PDP. A level shift circuit includes a CMOS circuit and drives the output buffer circuit. An electric charge recovery circuit connected to a power supply of the output buffer circuit recovers and reuses electric charges remaining on the data electrode after the discharge of the display cells. A power supply control circuit controls so that the power supply voltage of the level shift circuit is higher than the sum of the power supply voltage of the output buffer circuit and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazunari Takasugi
  • Patent number: 7829925
    Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Sakoh, Mami Toda
  • Patent number: 7829246
    Abstract: Formation of a constricted portion in an interconnect pattern is inhibited while moderating design rule for a phase shifting mask.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yukiya Kawakami
  • Patent number: 7829439
    Abstract: In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system generates a laser beam, and a movement system relatively moves the semiconductor wafer with respect to the laser beam such that the semiconductor wafer is irradiated with a laser beam along the scribe lines to partially remove the multi-layered wiring structure from the semiconductor wafer along the scribe lines. An irradiation control system controls the irradiation of the semiconductor wafer with the laser beam along the scribe lines such that the alignment mark is left on the scribe line.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tsuyoshi Kida
  • Patent number: 7830740
    Abstract: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Susumu Takano
  • Patent number: 7831939
    Abstract: In a semiconductor integrated circuit design method for carrying out a design of circuit patterns, a plurality of circuit patterns are defined, and each of the circuit patterns is composed of at least one minimum unit area. One of the circuit patterns is selected, and an expansion area is defined with respect to the selected circuit pattern so that the selected circuit pattern is at least included in the expansion area. An area ratio of an area size of the circuit pattern or circuit patterns included in the expansion area to an area size of the expansion area is calculated, and the area ratio is compared with a reference value.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihisa Matsubara
  • Patent number: 7830207
    Abstract: A differential amplifier circuit 110 composed of an inverter is connected to the power supply voltage VCC and the ground voltage GND through a NMOS transistor 142 and a PMOS transistor 144 respectively. The NMOS transistor 142 is connected to the control signal terminal PS, and the PMOS transistor 144 is connected to control signal terminal PS through an inverter 150. The NMOS transistor 142 and the PMOS transistor 144 are controlled such that they can be simultaneously cut off by a control signal from the control signal terminal PS. In this way, the power consumption of the amplifier is reduced.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Jia Chen
  • Patent number: 7825529
    Abstract: A semiconductor device includes a semiconductor substrate and an alignment mark. The alignment mark is provided on the semiconductor substrate and optically detectable. The alignment mark includes a bright area and a dark area. The bright area outputs light reflected from a surface of the semiconductor substrate. The dark area includes metal wirings, outputs light reflected from surfaces of the metal wirings, and has brightness lower than that of the bright area.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideaki Horii
  • Patent number: 7825705
    Abstract: A reset signal generating circuit outputs a reset signal having a sufficient pulse width even when the power supply voltage is fluctuated. A node B reaches a high level during a power-on reset and is at a low level during operation. When a power supply (Vcc) fluctuates during operation and as soon as a node C reaches a high level, a switch element MN50 turns on, the node B is decreased to a low level, and a stable low-level reset signal RST1 is outputted. When the node B reaches a low level, a switch element MN51 turns off with a delay and capacitors 104 and 105 are gradually charged by a charging circuit 112. When the potential at the node B exceeds a threshold level of an inverter circuit 106, the reset signal RST1 is brought back to a high level, the reset is cancelled, the switch element MN50 is turned off, and the switch element MN51 is brought to be in an on-state again (FIG. 1).
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kenichi Kawakita
  • Patent number: 7825725
    Abstract: Class D amplifier is resistant to interferences. Binary output signals y1 and y2, are generated from input signal s1, delivered to input terminal IN, to drive a load connected across output terminals OUTP and OUTN. Pulse generating circuit 10 generates a pulse width modulated pulse signal y0 from input signal s1, inverted signal of the output signal y1 and output signal y2. Differential pulse generating circuit 14 receives pulse signal y0 and inverts low and high levels of pulse signal y0, while shifting the resulting signal by half period from the pulse signal y0, to generate a pulse signal y3. Pulse amplifier 11a receives pulse signal y0 and generates output signal y1 supplied to output terminal OUTP. Pulse amplifier 11b receives pulse signal y3 and generates output signal y2 delivered to output terminal OUTN.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Terumitsu Komatsu
  • Patent number: 7825410
    Abstract: A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Osamu Mizoguchi
  • Patent number: 7825673
    Abstract: Failure analysis method includes performing fixed radiation of semiconductor chip (wafer) by photocurrent generation laser beam, scanning and radiating a region to be observed on semiconductor chip by heating laser beam, detecting, by a SQUID fluxmeter, current change generated in the semiconductor chip by radiating the photocurrent generation laser beam and the heating laser beam, and analyzing failure of the semiconductor chip based on current change detected by the SQUID fluxmeter. Radiation of photocurrent generation laser beam and heating laser beam are performed from a back surface side of the LSI chip, and detection by the SQUID fluxmeter is performed on a front surface side of the LSI chip. In analysis of failure of the LSI chip, image processing is performed in which a signal outputted from the SQUID fluxmeter is made to correspond to a scanning point. Visualization of defects is possible.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kiyoshi Nikawa
  • Patent number: 7826281
    Abstract: A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2 makes the DQS signal maskable with a mask signal MS.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hidemi Nakashima
  • Patent number: 7826479
    Abstract: A communication message conversion device according to the present invention comprises a first receiving unit receiving a first message according to a first communication protocol, a first message storage unit storing the first message received by the first receiving unit in one of a plurality of buffer areas according to a first message identifier contained in the first message, a first identifier conversion unit converting the first message identifier contained in the first message stored in the first message storage unit into a second message identifier, a first message conversion unit packing a plurality of first messages converted with the first identifier conversion unit into a second message and a first transmission unit transmitting the second message converted with the first message conversion unit according to a second communication protocol.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takashi Fujimori
  • Patent number: 7826186
    Abstract: When a manufacturing process becomes finer and a threshold value drops, a leakage current generates in a MOS transistor that is normally in an off-state. In order to suppress an influence of a leakage current that is generated in a protection transistor that constitutes a protection circuit on the internal circuit, an adjustor circuit that forms a transit path of the leakage current is disposed within the protection circuit, and a monitor circuit having the same circuit configuration as a configuration of the protection circuit is disposed to control an impedance of the transit path in the protection circuit and the monitor circuit so as to allow the leakage current to flow through the transit path.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masakazu Ikegami
  • Patent number: 7826261
    Abstract: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a natural number) contact plugs (32) are connected to a diffusion layer (22) of the FET (20) while n (n is a natural number) contact plugs (34) are connected to a diffusion layer (24). Here, m is smaller than n. The detection circuit (50) detects the difference between the output of the FET (10) and the output of the FET (20).
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Toshinori Fukai
  • Patent number: 7825471
    Abstract: A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shinobu Asayama
  • Patent number: 7825466
    Abstract: The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinao Miura, Hitoshi Ninomiya
  • Patent number: 7825727
    Abstract: An input stage of a differential amplifier includes a differential pair formed by an N-channel MOS transistor MN1 having a gate connected to an INM and an N-channel MOS transistor MN2 having a gate connected to an INP, both having sources connected to each other, a constant current source connected to the sources of the MN1 and MN2, and a variable current source connected to the sources of the MN1 and MN2. A subsequent-stage processing circuit having an intermediate stage and an output stage includes a phase compensation capacitor and outputs an output responsive to a change in the differential inputs by charging and discharging the phase compensation capacitor through the constant current source. The variable current source turns ON when the change reaches a level causing a parasitic capacitor at the sources of the differential pair to be discharged, and supplies a current for discharging the parasitic capacitor.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Shimatani
  • Patent number: 7826492
    Abstract: A communication system carrying out an isochronous transfer, includes a cycle master node and nodes connected with each other through a system bus. The cycle master node sets a cycle time of the isochronous transfer and transfers a cycle start packet onto the system bus for every the cycle time. Each of the nodes transfers an isochronous packet onto the system bus in response to the cycle start packet.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Junichi Takeuchi