Patents Assigned to NEC Electronics
  • Publication number: 20100265024
    Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 21, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 7816280
    Abstract: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 7817511
    Abstract: An embodiment of the present invention provides a phase difference detection circuit for detecting a phase difference between input data and an input clock generated based on the input data, including: an input data edge position detecting part detecting an edge position of the input data based on an N-phase clock obtained by dividing a predetermined period into N areas (N is an integer of 2 or more); an input clock edge position detecting part detecting an edge position of the input clock based on the input clock and the N-phase clock; and a phase difference detecting part detecting the phase difference between the input data and the input clock based on the edge position of the input data and an edge position of the input clock.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kenji Kobayashi
  • Patent number: 7816989
    Abstract: A differential amplifier includes a first differential pair formed by transistors of a first conductivity type, to receive input signals and output first differential-mode currents, a first current amplifier section to output a first output source current and a first output sink current to a first output terminal and a second output terminal, respectively, based on the first differential-mode currents, a second differential pair formed by transistors of a second conductivity type, to receive the input signals and output second differential-mode currents, and a second current amplifier section to output a second output source current and a second output sink current to the first output terminal and the second output terminal, respectively, based on the second differential-mode currents.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tachio Yuasa
  • Patent number: 7816782
    Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: October 19, 2010
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Hideya Murai, Tadanori Shimoto, Takuo Funaya, Katsumi Kikuchi, Shintaro Yamamichi, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata, Kouji Matsui, Shinichi Miyazaki
  • Patent number: 7816183
    Abstract: In the multiple-layered semiconductor device and the method for manufacturing thereof according to the present invention, the resin is formed on the substrate around the semiconductor device, on which the semiconductor device is installed in the first semiconductor package. Therefore, a generation of a warpage of substrate is inhibited in the first semiconductor package. And since the first semiconductor package is stacked to and coupled to the second semiconductor package via the electric conductors that extend from the back surface of the second semiconductor package to the coupling lands on the substrate penetrating through the resin, a defective situation such as a coupling defective in the bump junction can be avoided when the junction of the second semiconductor package via the electric conductor is formed. Therefore, a considerably improved coupling reliability in the multiple-layered semiconductor device can be achieved.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tsutomu Kawata
  • Patent number: 7818598
    Abstract: A semiconductor device provided on a semiconductor substrate having a cell placing area disposed on a semiconductor substrate, the cell placing area including a plurality of basic cells supplied with power from a local power supply line, a global power supply line to supply power to the local power supply line, at least one switch cell having a terminal electrically connected to the global power supply line, another terminal electrically connected to the local power supply line and a switch to turn on and off power supply from the global power supply line to the local power supply line and a repeater circuit disposed in the cell placing area, the repeater circuit supplied with power from the global power supply line without interposing the switch.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: October 19, 2010
    Assignee: Nec Electronics Corporation
    Inventor: Takefumi Hiraga
  • Patent number: 7818706
    Abstract: Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O 11b, supplied with a clock signal from outside, and a PLL 12, connected to the I/O 11b, and adapted for routing an internal clock signal, generated on the basis of the clock signal, to DRAM macros 14. The PLL 12 generates the internal clock signal by multiplying the frequency of the clock signal. The internal clock signal generated is distributed via buffer 13 to each macro cell in need of the internal clock signal. Part of the DRAM macros may be replaced by logic macro cells.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Junichi Nakata
  • Patent number: 7816213
    Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0<x?3 and 0<y?3, and x and y are different from each other.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takeo Matsuki
  • Patent number: 7817264
    Abstract: In a method for preparing focus-adjustment data for a focusing lens system of an optical defect-inspection apparatus, a wafer having a plurality of defects is positioned in place with respect to a focal plane defined by the focusing lens system at a positioning step, and the detects on the wafer are optically and electronically detected at a detecting step. Then, defects having a predetermined size are extracted among the detected defects at extracting step, and a number of the extracted defects is counted as defect-number data. The positioning, detecting, extracting and counting steps are repeated whenever the focus-adjustment wafer is relatively shifted from the focal plane by a predetermined distance, and a defect-number distribution is produced based on the defect-number data thus obtained.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kenichi Sanada
  • Patent number: 7817385
    Abstract: In a semiconductor device including two circuit blocks, an ESD protection circuit between power supply terminals (or ground terminals) of the two circuit blocks having the same voltage level as each other is constructed by at least one diode-connected field effect transistor whose back gate potential is adjusted by a back gate potential adjusting circuit. As a result, the absolute value of the threshold voltage and the ON resistance of the ESD protection circuit can be changed in accordance with whether the operation mode is an ESD protection operation mode or a usual operation mode.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: October 19, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Toshikatsu Kawachi
  • Publication number: 20100259860
    Abstract: An overvoltage protection circuit includes an output transistor coupled between a power supply and an output terminal, the output terminal including a terminal for being coupled to a load and a dynamic clamping circuit and a clamp selection transistor coupled in series between the power supply terminal and a control terminal of the output transistor. The clamp selection transistor is coupled between the dynamic clamping circuit and a control terminal of the output transistor. In addition, the clamp selector transistor includes an N-channel type transistor, a control terminal of the N-channel type transistor being coupled to a ground potential.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 14, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Osamu Souma
  • Publication number: 20100258799
    Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 14, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Akio Matsuoka
  • Patent number: 7812804
    Abstract: A drive circuit that is an example of the present invention is a drive circuit of a display device for outputting in parallel the analog picture signals generated based on the digital picture signals inputted in serial. This circuit comprises a level shift circuit for converting the voltage level of the digital picture signals that were inputted in serial, a D/A conversion circuit for generating analog picture signals based on the digital picture signals that were subjected to level conversion with the level shift circuit, and an expansion circuit connected to the output side of the D/A conversion circuit or between the level shift circuit and the D/A conversion circuit and serving to expand and hold the inputted serial picture signals in parallel and output the picture signals in parallel. The level shift circuit is thus formed in the front stage of the picture signal register circuit.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshiharu Hashimoto
  • Patent number: 7811920
    Abstract: The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are provided in the insulating film 105.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Satoshi Matsui
  • Patent number: 7812689
    Abstract: Disclosed is a microwave phase shifter including switches each of which utilizes resonance between an off-capacitance of an FET and an inductor connected in parallel with the off-capacitance of the FET, an LPF, and an HPF, a series circuit of an inductor and an MIM capacitor is arranged in parallel with the FET in each portion of the resonance. In a layout of the LC series-connected circuit, though the inductor is of a non-close-packed structure, a metal member or a dielectric material having a relative dielectric constant higher than that of a dielectric substrate is arranged in a free space in a central portion of the inductor.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takao Atsumo, Hiroshi Mizutani
  • Patent number: 7812752
    Abstract: A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Tsuchi, Noboru Okuzono
  • Patent number: 7812848
    Abstract: A memory device includes a memory and a control circuit. The memory includes cells arranged in a matrix of rows and columns. The cells are grouped into banks, and each of the banks contains at least one column of the cells. The control circuit instructs a read operation in units of rows and a write operation in units of cells, and inhibits the read operation in units of the banks when the write operation is carried out to a specific one of the cells of a specific one of the banks.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masumi Shiono
  • Patent number: 7814381
    Abstract: A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Ozeki
  • Patent number: 7811096
    Abstract: An IC socket is provided with first and second contact pins and a socket body supporting said first and second contact pins. The first contact pin is used to establish a connection with a first terminal of a semiconductor package, while the second contact pin is used to establish a connection with a second terminal of said semiconductor package. The first and second terminals have different heights from a mount face of the semiconductor package.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: October 12, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naohiro Takagi