Patents Assigned to NEC Electronics
  • Patent number: 7839370
    Abstract: A display panel driver is composed of a grayscale voltage generator configured to develop a set of different grayscale voltages corresponding to grayscale levels of pixels within a display panel; and a plurality of grayscale selector driver circuits each of which is responsive to pixel data to select one of the grayscale voltages, and to provide a drive voltage corresponding to the selected one of the grayscale voltages for a selected pixel within the display panel. The grayscale voltage generator is allowed to output the set of grayscale voltages during a first period within a horizontal period, and prohibited from outputting the set of grayscale voltages during a second period within the horizontal period.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masaki Izumikawa, Masayuki Kumeta
  • Patent number: 7840727
    Abstract: Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takanori Saeki, Yasushi Aoki, Masatomo Eimitsu, Masashi Nakagawa, Minoru Nishizawa, Tadashi Iwasaki, Koichiro Kiguchi
  • Publication number: 20100289684
    Abstract: Provided is an analog-digital converter circuit including: a comparison unit that sequentially compares an analog input voltage with reference voltages, which sequentially vary, and outputs a comparison result as a digital value; a standard voltage generation unit that generates a standard voltage for correcting the reference voltages; a storage unit that stores a comparison result of the standard voltage obtained by the comparison unit; and a reference voltage generation unit that generates the reference voltages based on the comparison result of the standard voltage.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 18, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Mamoru IKEDA
  • Publication number: 20100289526
    Abstract: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first conductivity type transistor having its gate receiving the first and second pulse signals respectively, its source connected to a ground, and its drain outputs a level shifted pulse signal, and a first transistor of a second conductivity type having its gate connected to the gate of the transistor of the first conductivity type, its drain connected to the drain of the transistor of the first conductivity type, and its source connected to the power supply via a connected transistor group, and the connected transistor group includes at least one of the second conductivity type transistors.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 18, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Hiroyuki Kuge
  • Patent number: 7834465
    Abstract: In a technique connecting between bonding pads of semiconductor chips, contact between wires is prevented. A semiconductor device of the present embodiment is provided with a semiconductor chip 1 in which a plurality of bonding pads 3 are arranged in line, a semiconductor chip 2 in which a plurality of bonding pads 4 are arranged in line substantially parallel to the plurality of bonding pads 3, and a plurality of wires 7 which connect the bonding pads 3 to the bonding pads 4 respectively. At least one of the wires 7 is bended with respect to a reference straight line S which passes through the bonding pad 3 and the bonding pad 4 which are connected by the wire 7. The bended wire is extended out from the bonding pad 4 in a certain direction in which a distance between the bended wire and an adjacent wire which is adjacent to the bended wire is larger than a distance between the reference straight line of the bended wire and the reference straight line of the adjacent wire.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tsutomu Sano
  • Patent number: 7834402
    Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer of D1 includes a projection plane of a region of an n+ diffusion layer of N, and a projection plane of a region of an n+ diffusion layer of the diode D2 includes a projection plane of a region of a p+ diffusion layer of P1.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideyuki Yoneda
  • Patent number: 7834670
    Abstract: An input circuit, includes a first buffer circuit having an output signal terminal connected to an output; a capacitor having one end connected to an input signal terminal, and the other end connected to an input of the first buffer circuit; a first differential amplification circuit receiving a voltage of a first external power source terminal and an output of a second buffer circuit; a second differential amplification circuit receiving a voltage of a second external power source terminal and an output of a third buffer circuit; a first resistance having one end connected to an output of the first differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit; and a second resistance having one end connected to an output of the second differential amplification circuit, and the other end connected between the capacitor and the first buffer circuit.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yuji Nakajima
  • Patent number: 7836375
    Abstract: An encoding device includes a buffer for performing EDC generation, scrambling and ECC generation on user data arranged along user data direction Q that is read out from a data buffer of SDRAM and storing the operation results, a substitution buffer for repeatedly reading out the user data by burst transfer from the data buffer and outputting the data in recording frame direction P, and a scrambler for scrambling the data output from the substitution buffer along the direction P according to the operation results and outputting scrambled data. The substitution buffer is configured by SRAM and has a memory capacity of equal to or larger than a minimum capacity to output user data in the direction P and smaller than a memory capacity of the data buffer.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takeo Ariyama
  • Patent number: 7834669
    Abstract: Between a control terminal (gate) of an output transistor of a source follower configuration and an output terminal to which a load is coupled, a depletion transistor having a relatively lower breakdown voltage (that is, smaller device-area) is provided as a shutdown transistor of the output transistor, to thereby control a conductive state/nonconductive state of the depletion transistor. There are provided: the output transistor of the source follower configuration coupled between a first power supply line and the output terminal; the load coupled between the output terminal and a second power supply line; the depletion transistor coupled between the gate of the output transistor and the output terminal; and a control circuit controlling the conductive state/nonconductive state of the depletion transistor by applying, between a gate and a source thereof, a voltage smaller than a voltage deference between a potential of the first power supply line and a potential of the second power supply line.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Akihiro Nakahara
  • Patent number: 7833901
    Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Patent number: 7833909
    Abstract: Aimed at suppressing roughening in a circumferential portion of a layer to be etched in the process of removing a hard mask formed thereon, an etching apparatus of the present invention has a process chamber, an electrode, a stage, and a shadow ring, wherein the process chamber allows an etching gas to be introduced therein; the electrode is disposed in the process chamber, and is used for generating plasma by ionizing the etching gas; the stage is disposed in the process chamber, onto which a substrate is disposed; the shadow ring has an irregular pattern on the inner circumferential edge thereof, and is disposed in the process chamber and placed above the stage 30, so as to cover a circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masahiro Komuro
  • Patent number: 7835185
    Abstract: A nonvolatile semiconductor memory device in accordance with the present invention is provided with a plurality of memory cells of field effect transistor type, a source bias control circuit, and a drain bias control circuit. The source bias control circuit variably sets the potential of a source line connected in common to the sources of the plurality of memory cells at the time of write operation. The drain bias control circuit variably sets the potential of the drains of the plurality of memory cells at the time of write operation according to the potential of the source line.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Sugawara
  • Patent number: 7834461
    Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Shuji Asai, Tadachika Hidaka, Naoto Kurosawa, Hirokazu Oikawa, Takaki Niwa
  • Patent number: 7836253
    Abstract: A cache memory arranged between a processor and a low-speed memory and performing a pipeline processing of a memory access made by the processor. In a first stage, the cache memory reads out a tag address from a tag memory. In a second stage, the cache memory performs a hit decision by a hit decision unit. When the hit decision result is a miss hit, the cache memory performs an update control of the tag memory and a behavior control of a bypass circuit for supplying a data held in a latch circuit to the hit decision unit by bypassing the tag memory in a third stage. The latch circuit is configured to hold a tag address included in a input address supplied from the processor.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Satoshi Chiba, Takumi Kato
  • Patent number: 7834390
    Abstract: A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the floating gate; a first device isolation structure having a first projecting portion; and a second device isolation structure having a second projecting portion. The first and second projecting portions have a first sloping surface and a second sloping surface, respectively. The first sloping surface and the second sloping surface face each other, and an interval between the first and second sloping surfaces becomes larger away from the semiconductor substrate. The floating gate is sandwiched between the first and second projecting portions and at least has a portion located on the semiconductor substrate side of the first and second sloping surfaces.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takaaki Nagai
  • Patent number: 7835211
    Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7834418
    Abstract: A semiconductor device (100) includes a semiconductor substrate (2), an inductor (4) provided on the semiconductor substrate (2), a metal ball (8) provided on the inductor (4) so as to come into contact with the inductor (4), and a bonding wire (10) electrically connected to the metal ball (8). The semiconductor device (100) exchanges signals with an external via the inductor (4) and the metal ball (8). The inductor (4) also serves as the bonding pad and therefore the inductor and the bonding pad need not to be arranged in pairs.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shinichi Uchida
  • Publication number: 20100283644
    Abstract: An A/D conversion circuit includes a plurality of transmission paths that transmit signal voltages and reference voltages, and an A/D conversion unit that A/D converts voltages output from the transmission paths. Each of the plurality of transmission paths includes a first switch that selectively outputs one of the signal voltage and the reference voltage, an S/H circuit that holds output voltage from the first switch, and a second switch that selectively outputs one of the output voltage from the first switch and output voltage from the S/H circuit.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 11, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Tomoya Katsuki, Shinichirou Saitou
  • Publication number: 20100283508
    Abstract: A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 11, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Hideo ISOGAI, Kentarou Tanaka
  • Patent number: 7829417
    Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura, Yoshiya Kawashima