Abstract: In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Abstract: An object of the present invention is to provide a highly accurate delta sigma A/D converter. Disclosed is a delta sigma A/D converter including: a first integration circuit to generate a first signal on the basis of an input signal and a first feedback signal from an output side; a first signal conversion circuit to convert the first signal into a first converted signal; a loop delay compensation circuit to generate a compensation signal and then to output the compensation signal in response to a second feedback signal fed back from the output side at a timing earlier than that of the first feedback signal; an adder circuit to add the first converted signal and the compensation signal; and a comparator to generate a digital signal on the basis of an output signal from the adder circuit. The loop delay compensation circuit includes a compensation signal conversion circuit to generate the compensation signal.

Abstract: A disconnection detecting method includes charging a capacitor by connecting a node of the capacitor to a first power source line supplied with a first power source potential, connecting the node of the capacitor to an input terminal, after the node of the capacitor is disconnected from the first power source line, and converting a first value on the node to a first digital data. The method further includes discharging the capacitor by connecting the node of the capacitor to a first power source line supplied with a second power source potential, after the node is disconnected from the input terminal, connecting the node of the capacitor to the input terminal, after the node of the capacitor is disconnected from the second power source line, and converting a second value on the node to a second digital data.

Abstract: A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages.

Abstract: Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point.

Abstract: To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix in each iteration, the order of message computation at a cluster in an iteration out of at least two iterations that have a before-and-after relationship in time and the order of message computation at a cluster in another iteration are varied.

Abstract: An SC-type optical receptacle includes a first and a second holder each having a hollow chamber longitudinally penetrating therethrough, and a hollow cylindrical sleeve fitted in the chamber of the holders to thereby retain the frontal facets of a pair of ferrules so as to keep the frontal facets butted to each other. The wall thickness of the sleeve is constant over the entire length thereof, and is not less than 0.55 mm.

Abstract: A method of operating a liquid crystal display device includes: (A) time-divisionally driving pixels in a certain line of an LCD panel so that pixels adjacent in a horizontal direction are driven with data signals of opposite polarities. The (A) step includes: (A1) generating a first data signal of a first polarity on a first output terminal of a driver, and then driving a first pixel out of said pixels in the certain line through electrically connecting the first output terminal to the first pixel; and (A2) generating a second data signal of the first polarity on the first output terminal and then driving a second pixel out of said pixels in the certain line through electrically connecting the first output terminal to the second pixel, in succession to the drive of the first pixel.

Abstract: A semiconductor device contains an interposer having a square planar geometry, with length X for a first edge and length Y for a second edge orthogonal to the first edge, and a semiconductor chip and a dummy component disposed over the interposer, wherein the center of a first outer circumferential region, which surrounds the semiconductor chip over the interposer, and has length “a” for a third edge, and length “b” for a fourth edge, does not coincide with the center of the interposer, or equation X:Y=a:b is not satisfied, and the center of a second outer circumferential region, which surrounds the first outer circumferential region and the dummy components disposed over the interposer, and has length “x” for a fifth edge, and length “y” for a sixth edge, coincides with the center of the interposer, and equation X:Y=x:y is satisfied.

Abstract: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state.

Abstract: A multi-source MOS transistor includes a sense MOS transistor and a load MOS transistor, and is connected to a load. A current detection portion has a negative input offset voltage characteristic, and detects a first sense current in a state where it is connected to the power supply and the sense MOS transistor and a second sense current in a state where it is connected to the sense MOS transistor and the load MOS transistor. A calculation control portion calculates a load current based on the first sense current and the second sense current such that the effect of the input offset voltage in the current detection portion is cancelled.

Abstract: A simulation system includes an input acceptance unit that accepts a measured dimension of a transfer pattern; a calculation unit including a light intensity calculation unit that calculates a light intensity at each position, and a modified light intensity calculation unit that adds a modified value including the product of the light intensity and a tentative optical reaction coefficient to the light intensity, thereby giving a modified light intensity; and a decision unit that decides the threshold value and optical reaction coefficient by regression calculation such that a difference between the measured dimension and the calculated dimension becomes minimal under the modified light intensity, with a constant being the threshold value of the light intensity at a pair of edges defining the calculated dimension of the transfer pattern in the simulation.

Abstract: An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiting time from a time the bus master outputs a memory access request until a time a connection between the bus master and the memory controller is established, and the memory controller controls a memory access based on the waiting time counted by the counter.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: In a conventional solid state imaging device, there is a room for improvement in sensitivity. In order to solve the problem, a solid state imaging device includes a semiconductor substrate and a light receiving portion. The light receiving portion is provided adjacent to a surface layer on the surface (a first surface) side of the semiconductor substrate. The surface of the light receiving portion is silicided. The solid state imaging device is one in which light from an object to be imaged incident on the back side (a second surface) of the semiconductor substrate is photoelectric-converted inside the semiconductor substrate, the light receiving portion receives electric charge generated by the photoelectric conversion, and the above mentioned object to be imaged is imaged.

Abstract: There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (101 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (101 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).

Abstract: In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a width larger than the uniform width. A bottom of a base region adjacent to the trench is adjacent to the second opening.

Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.

Abstract: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.

Abstract: A liquid crystal display apparatus is composed of an LCD panel including data lines, and an LCD driver. The LCD driver includes: a positive drive circuit providing a positive data signal having positive polarity with respect to a ground level of the LCD driver for one of the data lines; and a negative drive circuit providing a negative data signal having negative polarity with respect to the ground level of the LCD driver for another one of the data lines.