Patents Assigned to NEC Electronics
  • Patent number: 7825727
    Abstract: An input stage of a differential amplifier includes a differential pair formed by an N-channel MOS transistor MN1 having a gate connected to an INM and an N-channel MOS transistor MN2 having a gate connected to an INP, both having sources connected to each other, a constant current source connected to the sources of the MN1 and MN2, and a variable current source connected to the sources of the MN1 and MN2. A subsequent-stage processing circuit having an intermediate stage and an output stage includes a phase compensation capacitor and outputs an output responsive to a change in the differential inputs by charging and discharging the phase compensation capacitor through the constant current source. The variable current source turns ON when the change reaches a level causing a parasitic capacitor at the sources of the differential pair to be discharged, and supplies a current for discharging the parasitic capacitor.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: November 2, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Shimatani
  • Publication number: 20100272142
    Abstract: Provided is a semiconductor laser element having a first protective film provided at least over the light emitting end face of an active layer (3-period multiple quantum well (MQW) active layer); and a second protective film provided over the first protective film, wherein, the first protective film is provided between a semiconductor which composes the light emitting end face and the second protective film, and a portion of the first protective film, brought into direct contact with the semiconductor, is mainly composed of a rutile-structured TiO2 film.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 28, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kazuhisa Fukuda
  • Publication number: 20100273401
    Abstract: A polishing apparatus includes a polishing table with a polishing pad at an upper surface, and a conditioning disc carrying out conditioning of the polishing pad, and a moving mechanism (constructed, for example, from a swing arm) capable of moving the conditioning disc to a standby position above the polishing pad, and a spraying mechanism (constructed, for example, from a washing water nozzle) that sprays liquid to the conditioning disc positioned at the standby position so as to wash or wet the conditioning disc.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 28, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Masafumi Shiratani, Shigeyuki Yoshida, Osamu Ito
  • Publication number: 20100270643
    Abstract: Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 28, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Takayuki Iwaki
  • Publication number: 20100270683
    Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 28, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Publication number: 20100270677
    Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 28, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 7821101
    Abstract: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Daisuke Oshida, Takuji Onuma
  • Patent number: 7821037
    Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takaki Niwa, Naoto Kurosawa
  • Patent number: 7821135
    Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazuyoshi Ueno
  • Patent number: 7820489
    Abstract: A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to establish electrical connection.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takekazu Tanaka, Kouhei Takahashi
  • Patent number: 7819723
    Abstract: To provide a retainer ring by which an object to be polished can be uniformly polished, and deterioration thereof can be suppressed, and it does not take time to recycle, and a polishing machine having the retainer ring. The retainer ring 1 includes: a first annular portion 11 for surrounding an outer circumferential portion of the object to be polished and made of resin; and a second annular portion 12 provided on the first annular portion 11 and having a mechanical strength higher than that of the first annular portion 11. In rim portions of the first annular portion 11 and the second annular portion 12, a fixing portion 13 for fixing the first annular portion 11 and the second annular portion 12 with mechanical joining is provided. The first annular portion 11 protrudes beyond the fixing portion 13 toward the opposite side of the second annular portion 12.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhiko Nakamura
  • Patent number: 7821823
    Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Sunamura, Kouji Masuzaki, Masayuki Terai
  • Patent number: 7821115
    Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Chihiro Sasaki, Yasuaki Iwata
  • Patent number: 7822152
    Abstract: A symbol timing detection method, executed in a processor, is provided where, upon detecting a symbol timing from a received signal composed of a packet having a preamble with periodically allocated symbols placed at a head of data, correlation results indicating a correlation between the received signal and a fixed pattern of the preamble are obtained, a maximum value in the correlation results are updated and held, and a timing of the maximum value is determined as a symbol timing on a condition that a maximum value currently held by the correlation peak detection unit is not updated in a symbol timing determination period having a predetermined length from the timing and that a number of occurrences of a correlation result exceeding an error detection determination threshold is smaller than a predetermined number in an error detection determination period defined within the symbol timing determination period.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Osamu Inagawa, Junya Tsuchida
  • Patent number: 7822168
    Abstract: Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an o
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masafumi Mitsuishi
  • Patent number: 7821815
    Abstract: Conventional semiconductor memory devices have a problem of a data read failure caused by a leak current. To address this problem, a semiconductor memory device of the present invention including memory cells each formed of a transfer transistor, a load transistor and a drive transistor. Each of the memory cells includes: a first transfer transistor connected to a connection point of the drive transistor and the load transistor; a second transfer transistor connected between the first transfer transistor and a bit line DB; and a compensation transistor connected between a constant voltage node and a connection point of the first transfer transistor and the second transfer transistor. The compensation transistor is switched to a conductive state exclusively from at least one of the first transfer transistor and the second transfer transistor.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shinobu Asayama
  • Patent number: 7822094
    Abstract: A semiconductor laser element realizes a high COD light output in broader range of reflection factor at a facet with high reliability. A semiconductor laser element has a multi-layered reflection film formed on at least one end facet of a resonator. An optical path length of each layer of said multi-layered reflection film is determined by (2m?1)ยท?/4, where ? is oscillation wavelength, and m is positive integer). A high-refractive-index layer and a low-refractive-index layer are alternately stacked starting from a first layer adjacent to said semiconductor.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shin Ishikawa
  • Patent number: 7821817
    Abstract: In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semiconductor storage device according to one aspect of the present invention includes a third transistor having one of a source and a drain connected to a first bit line and switching supply of a ground voltage performed on the first bit line in accordance with a value held in a memory cell according to selection and non-selection of the memory cell, and a fixed voltage keeping circuit keeping a potential of the other of the source and the drain of the third transistor to a fixed potential in a memory cell non-selected state in a six-transistor SRAM.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shinobu Asayama
  • Patent number: 7821334
    Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tadashi Maeda, Tomoyuki Yamase
  • Patent number: RE41880
    Abstract: A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an address transition detector for detecting transition in input of addresses by which a memory cell is selected among the memory cells, and transmitting an address transition detecting signal indicative of the detected transition, (d) a counter for counting the address transition detecting signals, and (e) a reference cell decoder for selecting a reference cell among the reference cells in accordance with an output transmitted from the counter.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kiyokazu Hashimoto, Hiroshi Furuta