Abstract: A data recording/reproducing apparatus according to an embodiment of the present invention includes: a temporary storage unit for storing a data stream including a plurality of data units, which is divided into M (M is a natural number) segments that stores the plurality of data units; a control unit for detecting that K (K is a natural number) data units related to the order of reproducing or recording data of a first data unit, after the first data unit included in the data stream is stored in the temporary storage unit, and setting relational information for the K data units in the first data unit; and a recording/reproducing unit that receives a data stream including the set first data unit from the temporary storage unit on a segment basis, and references the received data stream to generate recording data to record the data on a recording medium, and/or reads the recorded data from the recording medium to reproduce the read data.

Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.

Abstract: To provide a driver circuit that enables reduction in the number of elements formed through a high-voltage process and in chip size. An embodiment of the present invention relates to a driver circuit for inversion-driving a liquid crystal display panel, including: a positive-polarity line transmitting a positive display signal relative to a common electrode signal; a negative-polarity line transmitting a negative display signal relative to the common electrode signal; a dot inversion switch circuit switching the positive-polarity line and the negative-polarity line from each other to be connected with a source line; a charge recovery circuit connected with the positive-polarity line through a positive charge recovery switch and connected with the negative-polarity line through a negative charge recovery switch; and a common short circuit connecting the positive-polarity line and the negative-polarity line with a common electrode.

Abstract: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an SOI substrate, is constituted by comprising an insulating layer 34, and a silicon layer 36, which is provided on the insulating layer 34, including a circuit forming region A1. The insulating layer 34 functions as a protective film (a first protective film) covering a lower face (a face opposite to the semiconductor chip 10) of the circuit forming region A1. A protective film 38 (a second protective film) is provided on the semiconductor substrate 22. The protective film 38 covers a side face of the circuit forming region A1.

Abstract: A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Abstract: A page table management circuit includes a memory control circuit including a memory unit that stores information used to convert a virtual address into a physical address with respect to each entry and designating the entry according to an input address value, and an address conversion circuit converting an input address value such that a total number of the entries to be designated by the memory control circuit is reduced and outputting the converted address value to the memory control circuit.

Abstract: A semiconductor device includes a field-effect transistor on a substrate. The field-effect transistor includes a gate insulating film and a gate electrode. The gate electrode has a laminated structure including a first electrode layer made of a first metal, a second electrode layer made of a second metal, and a third electrode layer made of a silicon layer. The second metal is a material having a workfunction for alleviating band discontinuity between the first electrode layer and the third electrode layer, with respect to a majority carrier of the silicon layer.

Abstract: A first mobile terminal forming a mobile communication system connects to a base station by using a first wireless communication method (for example, GSM method). Further, a second mobile terminal acquires unique information of the base station (for example, cell information) from the first mobile terminal by communication with the first mobile terminal by using a second wireless communication method (for example, wireless LAN method), and searches a transmission frequency of the base station included in the unique information.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.

Abstract: The solid-state imaging device includes a semiconductor substrate and a light receiving portion. On the back surface of the semiconductor substrate a contact surface is provided. The solid-state imaging device photoelectrically converts, in the semiconductor substrate, light transmitted through the object to be imaged in contact with the contact surface, and receives the electric charge generated by the photoelectric conversion with the light receiving portion, to thereby acquire the image of the object to be imaged. The contact surface is a rough surface.

Abstract: An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an upper electrode being in contact with the first trench-type insulating region and formed on the lower electrode with the first insulating film interposed therebetween; and a gate electrode being in contact with the second trench-type insulating region and formed on a channel region with the second insulating film interposed therebetween, in which a shape of at least a part of an end of the lower electrode forming region in contact with the first insulating film is sharper than a shape of an end of the channel region in contact with the second insulating film.

Abstract: A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer.

Abstract: A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the ECC circuit when a data width of the write data is less than a predetermined data width.

Abstract: To provide a semiconductor device capable of securely executing a reading operation to improve a reliability of read data, an IC tag including the semiconductor device, and a control method for the IC tag. A semiconductor device according to an embodiment of the present invention includes: a power supply voltage generating circuit for generating a power supply voltage based on a received radio signal; a power supply voltage generating circuit for detecting the power supply voltage; a memory area for storing predetermined data; a reading/writing circuit using different operation voltages for reading data from the memory area and writing data to the memory area; and a control circuit for executing a data reading operation for the memory area based on a detected power supply voltage.

Abstract: A lateral MOSFET according to the present invention has a trench gate structure having a cross sectional shape spreading toward an open end. The cross sectional shape is T-shape. The T-shaped cross section has a dimensional ratio of a width of a lower trench having a narrow width to a width of an upper trench having a wide width of 1:3, and a dimensional ratio of a depth of the lower trench to a depth of the upper trench of 1:1, the lower trench width having a same central axis as the upper trench width.

Abstract: An evaluation pattern for evaluation of lateral hillock formation is provided with a lattice pattern; and an isolated metallization. The lattice pattern includes: a loop interconnection; and lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns. The width of the lattice interconnections is narrower than the width of the loop interconnection. The isolated metallization is provided in an outmost one of the sub-regions, the outmost one being surrounded by the loop interconnection and corresponding ones of the lattice interconnections.

Abstract: A data line driving circuit includes a first buffer circuit configured to drive a data line, and a second buffer circuit configured to drive a data line. N first data lines (n is a natural number larger than 1), and m second data lines (m is a natural number larger than 1) are alternately arranged in units of data lines as a group. The data line driving circuit further includes a first switch circuit configured to select one of the n first data lines in a first ON period and to connect the selected first data line with the first buffer circuit, and a second switch circuit configured to select one of the m second data lines adjacent to the selected first data line in a second ON period and to connect the selected second data line with the second buffer circuit.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.

Abstract: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.