Abstract: Aimed at providing an ion implantation apparatus elongated in period over which failure of a target work, due to deposition and release of ion species typically to and from the inner surface of a through-hole shaping a beam shape of ion beam, may be avoidable, reduced in frequency of exchange of an aperture component, and consequently improved in productivity, an aperture component shaping a beam shape has a taper opposed to the ion beam, in at least a part of inner surface of at least the through-hole, and has a thick thermal-sprayed film formed so as to cover the inner surface and therearound of the through-hole.

Abstract: According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Abstract: A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and supplies a test signal input from an external terminal to the access terminal to thereby test the memory circuit. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed.

Abstract: A phase shifter according to an embodiment of the present invention includes: an AC component amplifying unit; and a dividing circuit. The AC component amplifying unit has positive gain slope characteristics and deforms a waveform of an input differential clock signal to output the deformed differential clock signal. The dividing circuit includes a T-flipflop having two D latches connected in series and receives the deformed differential clock signal defoemed by the AC component amplifying unit to generate at least two output signals having a phase difference of 90 degrees with a frequency of ½ of the deformed differential clock signal.

Abstract: The level shift circuit that converts a level of an input signal into a level between a first and a second voltage, which is higher than the first voltage includes a select circuit that generates an oscillation signal, where at least a frequency or an amplitude of the oscillation signal changes according to an input signal, a filter circuit that removes a DC component of the oscillation signal output from the select circuit and outputs an AC component, a detect circuit that operates between the first voltage and an output side voltage of the filter circuit, and generates a control signal including a signal voltage that changes according to at least a frequency or an amplitude of the AC component of the oscillation signal, and an output circuit that generates an output signal having a level between the first voltage and the second voltage according to the control signal.

Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.

Abstract: An electrostatic protective circuit includes a bipolar transistor, a bipolar transistor and an FET. The bipolar transistors and are coupled in series between a signal line and the ground (GND). The FET is configured that a source and a bulk thereof are coupled to a node N situated between the bipolar transistors, a gate is coupled to the signal line, and a drain is coupled to the power supply.

Abstract: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node data in a memory in a save mode; and a backup control circuit configured to supply to the target circuit, a system clock signal in the normal mode, a test clock signal in the scan path test mode, and a save/recover clock signal in the save mode, and to control the target circuit and the memory such operations in the normal mode, the scan path test mode, and the save mode are performed. The test clock signal is slower than the system clock signal, and the save/recover clock signal is slower than the system clock signal and faster than the test clock signal.

Abstract: A driver circuit of a display device according to an embodiment of the invention includes: a dot-inversion switch selectively supplying a driving voltage generated with an operational amplifier to a first pixel electrode or a second pixel electrode, the dot-inversion switch including: an operational amplifier-side switch and a pixel-side switch supplying the driving voltage to the first pixel electrode or the second pixel electrode; and a common short-circuit switch connected to a node between the operational amplifier-side switch and the pixel-side switch to supply an intermediate potential to the node.

Abstract: A successive approximation type A/D converter includes a main capacitance array connected with a common connection node; a correction capacitance array; a voltage comparator configured to detect a voltage of the common connection node; and a successive approximation register in which a value is set based on an output of the voltage comparator. A first control circuit changes voltages applied to capacitance elements of the main capacitance array and the correction capacitance array based on a value set in the successive approximation register. A second control circuit responds to a control signal to connect the main capacitance array to an input voltage signal or a first predetermined voltage, and the correction capacitance array to the common connection node or a second predetermined voltage.

Abstract: A teaching apparatus and a teaching method that facilitates accurately setting a retainer at a target position, and minimizes troublesome steps in the manufacturing process, are to be provided. The teaching apparatus includes a first member held by the retainer of the carrying apparatus, a second member attached to the wafer boat (mounting rack) so as to oppose the first member held by the retainer when the retainer is set close to the target position, an output unit, and an arithmetic unit. The first member includes a distance sensor that generates a sensor signal representing a distance between the distance sensor and a surface of the second member opposing the first member. On the surface of the second member opposing the first member, a reference mark A is provided. The first member includes an imaging device that shoots an image including the reference mark A, and generates image data.

Abstract: The present invention aims to provide a USB host controller capable of reducing time for a data transfer between storage devices. A USB host controller according to the present invention includes a buffer memory for USB pipe having a first buffer memory region and a second buffer memory region, and a buffer memory controller configured to control a data transfer between the buffer memory for USB pipe and each of first and second devices. The buffer memory controller stores data from the first device in the first buffer memory region, swaps address information corresponding to the first buffer memory region and address information corresponding to the second buffer memory region, and transfers data stored in the first buffer memory region to the second device, on the basis of the address information corresponding to the first buffer memory region after the swapping.

Abstract: Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device (1) includes: a first electrode (4) including a first semiconductor layer which protrudes with respect to a plane of a substrate; a side surface insulating film (5) formed on at least a part of a side surface of the first electrode (4); an upper surface insulating film (6) formed on the first electrode (4) and the side surface insulating film (5); and a second electrode (7) which covers the side surface insulating film (5) and the upper surface insulating film (6). The first electrode (4), the side surface insulating film (5), and the second electrode (7) constitute a capacitor element. A thickness of the upper surface insulating film (6) between the first electrode (4) and the second electrode (7) is larger than a thickness of the side surface insulating film (5) between the first electrode (4) and the second electrode (7).

Abstract: In the conventional bus control system, the interconnect section and the bridge section have the arbitration function. Meanwhile, the interconnect section and the bridge section were designed by different designers. Accordingly, a large number of man-hours are needed not only for designing the bridge section but also for inspecting the bridge section.

Abstract: In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.

Abstract: Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P1 and P2 and gate electrodes of the load transistors PL1 and PL2 are connected at the node 1 and the node 2. A source electrode of the additional transistor P1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S1 and S2 to the H level in other times than data write so that the additional transistor P1 or P2 compensates the load transistor PL1 or PL2, thereby increasing the static margin.

Abstract: Method and apparatus for precisely removing dusts from a side edge of a wafer, improving a production yield of wafers, and reducing a manufacturing cost for semiconductor devices. The apparatus includes: a retaining table having a circular top plan view, capable of retaining the wafer disposed on the top surface, and being rotated in the wafer cleaning; a feeding unit for supplying a cleaning solution to a top surface of the wafer; a cup member for recovering the cleaning solution supplied to the wafer, the cup member surrounding a radially outer circumference and a bottom of the retaining table; and a guard member disposed inside the cup member so as to be spaced apart from the retaining table, which surrounds the radially outer circumference of the retaining table.

Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Abstract: There is provided a semiconductor storage device having a memory cell including a transfer transistor, a load transistor and a drive transistor, which includes a first transfer transistor to become conductive by a potential applied to a first word line placed in parallel with a pair of bit lines, a second transfer transistor to become conductive by a potential applied to a second word line placed orthogonal to the pair of bit lines, and a control circuit to output a control signal for controlling the potentials of the first word line and the second word line in such a way that the first transfer transistor becomes conductive earlier than the second transfer transistor when setting both of the first transfer transistor and the second transfer transistor to a conductive state.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during silicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.