Abstract: A pair of memory nodes, a capacitor of which one end is connected to the memory nodes, and a switch part which is connected to the other end of the capacitor, and changes a connection state of the other end of the capacitor when a semiconductor memory device operates at a speed not lower than a predetermined speed are included. By changing the connection state of the other end of the capacitor in accordance with the operation state of the semiconductor memory device like this, the influence which the capacitor connected to the memory node exerts on the operation speed of the semiconductor memory device can be suppressed.

Abstract: In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during silicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.

Abstract: A buried semiconductor laser exhibiting a reduced dislocation of a contact layer is achieved. A buried semiconductor laser, comprising: an n-type indium phosphide (InP) substrate; an active layer disposed on the n-type InP substrate; block layers provided so as to bilaterally disposed on both sides of the active layer; a clad layer provided so as to cover the active layer and the block layers; and a p-type gallium indium arsenide (InGaAs) contact layer provided on the clad layer, wherein the p-type InGaAs contact layer has a compressive strain.

Abstract: Provided is a power supply control apparatus including an overcurrent detection circuit with enhanced overcurrent detection accuracy. A power supply control apparatus according to the present invention includes: an output transistor Q1 that controls a current to be supplied to a load; a voltage control circuit that applies a control voltage to a control terminal of the output transistor Q1; and an overcurrent detection circuit. The overcurrent detection circuit includes: a detection MOS transistor Q2 that generates a detection current according to a current flowing through the output MOS transistor Q1; a transistor 9 that generates a current Iref1 based on a bias signal BS1; a transistor 10 that generates a current Iref2 based on a bias signal BS2 that is different from the bias signal BS1, the transistor 10 having a size that is the same as that of transistor 9; and a current mirror circuit that outputs an overcurrent detection signal based on the current Iref1, the current Iref2 and the detection current.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.

Abstract: In a semiconductor device, a delaying circuit is configured to delay an input signal based on an internal setting data to output as a timing signal. A delay determining section is configured to determine a delay state of each of a plurality of delay signals obtained by delaying the timing signal, based on the plurality of delay signals. A program section is configured to change the internal setting data based on the delay state.

Abstract: A synchronization timing detecting apparatus includes a correlation calculator configured to generate a first correlation value by calculating a cross-correlation between an input signal being sampled and a reference signal or an auto-correlation of the sampled input signal, an interpolation processor configured to generate a second correlation value interpolating a plurality of the first correlation values having a different combination of sampling points of the input signal, and a detector to detect a synchronization timing based on the first and the second correlation values.

Abstract: A display device is provided with a display panel, a data line driving circuitry, and a scan line driving circuitry. The display panel includes: a plurality of data lines extending in a column direction; a plurality of scan lines extending in a row direction; a plurality of pixels disposed at respective intersections of the plurality of data lines and the plurality of scan lines, and a dummy data line arranged in parallel to the plurality of data lines. The data line driving circuitry drives the plurality of data lines and the dummy data line. The scan line driving circuitry drives the plurality of scan lines. The data line driving circuitry feeds a dummy signal to the scan line driving circuitry through the dummy data line. The scan line driving circuitry drives the scan lines in response to the dummy signal.

Abstract: Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device 100 involves irradiating the marking film 21 with an energy beam through the transparent protective film 31 after the protective film 31 is formed, and such irradiation causes a chemical modification of the material of the marking film 21 to create the marks. According to the above-described process for manufacturing the semiconductor device 100, the region for the marking or the upper surface of the marking film 21 is sheathed by the protective film 31, so that a damage to the semiconductor chip 11 due to the generations of dust, exothermic heat, gas, stress or the like during the marking operation can be reduced. This allows achieving the process for manufacturing the semiconductor device 100 that provides a manufacture of better quality of the marks.

Abstract: A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on.

Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.

Abstract: In a method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within one circuit block, at least one dummy gate pattern is formed in parallel with the gate patterns when a pitch between said gate patterns is larger than a predetermined maximum pitch, so that pitches between the gate patterns including the dummy gate pattern are smaller than the predetermined maximum pitch. Then, a photolithography process is performed upon the photoresist layer by using a phase shift photomask having first and second openings whose difference in phase is ?. The first and second openings alternate between the gate patterns including the dummy gate pattern to form phase edges therein.

Abstract: Disclosed is a multiplier circuit including first and second squaring circuits comprising first and second differential MOS transistors respectively connected in cascode to first and second diode-connected MOS transistors. The first squaring circuit receives a differential sum voltage of a first input voltage and a second input voltage. The second squaring circuit receives a differential subtraction voltage of the first input voltage and the second input voltage. Outputs of the first and second squaring circuits are first and second terminal voltages of the first and second diode-connected MOS transistors. A differential voltage between the first and second terminal voltages corresponds to the product of the first and second input voltages.

Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, wherein the method facilitates obtaining a full silicide phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.

Abstract: An interpoly insulating film is modified in the film quality, while preventing generation of trap sites. A floating gate 101 is provided on a channel-forming region in the vicinity of the surface of a silicon substrate 112, an interpoly insulating film 134 is provided so as to contact with the floating gate 101, and a control gate 103 is provided so as to contact with the interpoly insulating film 134 and so as to be opposed to at least a part of the floating gate 101. A process step of providing the interpoly insulating film 134 further includes a step of forming on the floating gate 101, the interpoly insulating film 134 so as to contact with the floating gate 101, and a step of exposing, subsequently to the formation of the interpoly insulating film 134, the interpoly insulating film 134 to an atmosphere containing a nitrogen-containing gas and oxygen, to thereby simultaneously proceed nitriding and oxidation of the interpoly insulating film 134.

Abstract: A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes the first output signal based on the first selection control signal. A second flip-flop of the plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes the second output signal based on a second selection control signal. The semiconductor integrated circuit device further includes a control circuit configured to generate the first and second selection control signals such that a period during which the first flip-flop fixes the first output signal is different from a period during which the second flip-flop fixes the second output signal.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.