Abstract: A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data to a memory through said first delaying circuit; and a data read circuit configured to read said write data written in said memory, as said read data through said second delaying circuit. A control circuit is configured to detect positions of a start edge and end edge of an eye opening which is formed based on fluctuation of said write data or said read data, to specify an intermediate position of the start edge and the end edge, and to determine a phase of a data strobe signal based on a difference between the intermediate position and one of the start edge and the end edge.

Abstract: A semiconductor device and a defect analysis method of a semiconductor device, in which a failure location can be easily identified. The semiconductor device is provided with at least 2N resistor patterns having a fixed form, and being divided into N groups; the resistor patterns of each group are disposed in parallel, in sequence, and at an equal pitch, so that (N?1) resistor patterns of another group interpose between a resistor pattern of each of the groups and another resistor pattern within the group in question; the resistor patterns of each of the groups is connected in series with other resistor patterns with the group; and the resistor patterns of each of the groups, which are connected in series, are additionally connected in series to resistor patterns of another group. Measuring pads are provided respectively between two ends of resistor patterns that are connected in series, and groups.

Abstract: Provided is a semiconductor laser including: a substrate (semiconductor substrate); an optical waveguide (active layer waveguide) with a mesa structure that includes an active layer (strain-compensated multiple quantum well active layer) including Al, is provided over the semiconductor substrate; a semiconductor protective layer that is provided so as to cover the top and the side of a mesa of the active layer waveguide; a current block layer that is provided so as to embed the active layer waveguide and the semiconductor protective layer; and a clad layer (p-type InP clad layer) that is provided over the semiconductor protective layer and the current block layer, wherein, the semiconductor protective layer has a semiconductor layer (p-type InGaAsP protective layer) that includes As, but does not include Al.

Abstract: In order to provide a memory controller capable of calibrating a memory access timing even in a case where an application has no blanking interval, the memory controller includes: a delay circuit (3) for delaying data strobe signals; at least two FIFO buffer units (7, 8, and 9) for storing data values of data signals transmitted from a memory based on at least two of the data strobe signals delayed by the delay circuit (3), respectively; a comparator (4) for comparing the data values stored in the at least two FIFO buffer units; and a control circuit (6) for controlling delay time periods for the at least two of the data strobe signals by using the delay circuit (3) based on comparison results (10) acquired from the comparator (4). Further, one of the data values stored in the at least two FIFO buffer units is used also for normal operation.

Abstract: Error occurrence is predicted before the error occurs. Included are: a clock regeneration circuit (11) that regenerates, from a data input signal (Din), a clock signal (CK1) related to the data input signal (Din); a sampling clock generation circuit (12) that generates one or more sampling clock signals (CK2 and CK3) that are synchronous with the regenerated signal (CK1) and have a constant phase difference with respect to the regenerated clock signal (CK1); a sample and hold circuit (13) that samples and holds the data input signal (Din) according to the one or more sampling clock signals (CK2 and CK3) and the regenerated clock signal (CK1) respectively; and an error determination circuit (14) that outputs an error prediction signal (Ep) in a case where logical values of respective sampling results of the sample and hold circuit (13) are not all identical.

Abstract: An image stabilization apparatus of the present invention includes a detection unit which detects an amount of an image blur between a plurality of image data, an evaluation unit which selects at least one image data to use in correcting image blur from the plurality of image data according to a result of the detection of the amount of image blur, and a correction unit which generates image data with its image blur corrected using the image data selected by the evaluation unit.

Abstract: A level shifter is operated at high speed. An input unit 2 generates a first one-shot pulse signal at the rise of an input signal and a second one-shot pulse signal having the same polarity as the first one-shot pulse signal at the fall of the input signal, and eliminates the generated first and second one-shot pulse signals using an output signal. A level shift unit 3 includes a level shift circuit LS1 that converts the signal level of the first one-shot pulse signal and a level shift circuit LS2 that converts the signal level of the second one-shot pulse signal. An output unit 4 is driven corresponding to the first and second one-shot pulse signals whose levels have been shifted and generates the output signal. A hold unit 1 maintains the level of the generated output signal.

Abstract: A mail sending and receiving unit provided to a terminal for person in charge receives inquiry mails to which uniquely identifiable receipt numbers are added, and reply mails sent in response to the inquiry mails. An e-mail storage unit stores the incoming e-mails received by the mail sending and receiving unit, and the receipt numbers added to the incoming e-mails. The mail sending and receiving unit sends reply e-mails which are created in response to the incoming e-mails stored in the e-mail storage unit, and to which the receipt numbers of the corresponding incoming e-mails are added. A management screen generation unit displays the inquiry mails stored in the e-mail storage unit, and the reply mails, as being associated with each other by use of the receipt numbers of the respective inquiry mails.

Abstract: A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with said parity bit held in said register, and to issue a parity error interrupt when a parity error is detected. A parity bit inverting circuit inverts said parity bit held in said register in response to completion of said parity check.

Abstract: An object of the present invention is to improve safety of a motor by instantaneously detecting the abnormality of a PWM signal. To achieve the object, provided is a motor control microcomputer for outputting PWM signals to a motor drive circuit driving a motor, which includes an abnormal signal detection circuit and a PWM signal stop circuit. The abnormal signal detection circuit receives inputs of positive-phase and negative-phase signals of the PWM signals, detects that both of the positive-phase and negative-phase signals are at the H level, and then outputs detection signals. The PWM signal stop circuit receives the detection signals from the abnormal signal detection circuit, and stops the outputs of the PWM signals.

Abstract: Provided is a semiconductor device determining connection status between an output terminal connected to an output buffer and an external device, the semiconductor device including a test voltage generating circuit to generate test voltage for changing voltage of the output terminal, a connection detection determining circuit to compare voltage of the output terminal with reference voltage and to determine connection status of the external device based on the comparing result, and a compensation circuit generating simulation current where leak current generated at the output buffer is reproduced in a simulatory manner and compensating voltage change of the output terminal by the simulation current.

Abstract: An information processing apparatus according to an embodiment of the present invention includes: a CPU; a plurality of peripheral devices connected to the CPU through a bus; and a peripheral access protection setting unit storing access protection information representing whether an access to each of the peripheral devices is permitted or inhibited in accordance with a task to be performed by the CPU, wherein an access by the CPU to the peripheral devices is limited based on the access protection information and address information of the peripheral device.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Abstract: An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers; and a charge storage layer formed in the insulating film. A direction from the first N-type diffusion layer to the second N-type diffusion layer is the same as a crystal orientation <100> of the P-type silicon layer. At the time of rewriting, the hot holes go over a potential barrier of the insulating film to be injected into the charge storage layer.

Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.

Abstract: To prevent the value of a successive approximation register, which should be holding the value of the comparison result, from changing due to noise or the like during the A/D conversion by a successive approximation A/D converter, a detection circuit is arranged on an arbitrary bit of a successive approximation register 5 to detect the change in the value of the bit. The detection circuit detects the change in the value during the period in which the successive approximation register should be holding the data, such as during the period other than the comparison time, and outputs an abnormal conversion detection signal.

Abstract: The semiconductor apparatus includes a semiconductor chip, and a source electrode and a gate electrode which are formed on the semiconductor chip and electrically connected with a lead frame. The source electrode is electrically connected with the lead frame by being laser-welded with a thin-film shaped connecting portion formed at an end of the lead frame. This enables the provision of a semiconductor apparatus with enhanced productivity and yields which exhibits high electrical operability and reliability.

Abstract: When a convolution code is decoded, electric power consumption is suppressed keeping error correction capability. In a Viterbi decoder which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit estimates quality of the received signal and outputs a control signal according to the quality to a branch metric calculation data obtaining unit. The branch metric calculation data obtaining unit performs logical combination operation between digital multi-value data expressing amplitude of the received signal and the control signal, and thereby, outputs the digital multi-value data directly to a decoding execution unit if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data reduced by series each as branch metric calculation data to the decoding execution unit if the quality of the received signal is no less than the prescribed level.

Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.

Abstract: An overvoltage protection circuit includes an output transistor connected between a first power supply and an output terminal, a load connected to the output terminal, a dynamic clamping circuit for controlling a voltage difference between the first power supply and the output terminal, and a clamp selection switch electrically connected between the dynamic clamping circuit and the output terminal, and a conductive condition of the clamp selection switch is determined according to a comparison between a reference voltage and a voltage of the output terminal.