Patents Assigned to NEC Electronics
  • Patent number: 7768752
    Abstract: An overvoltage protection circuit includes an output transistor connected between a first power supply and an output terminal, a load connected to the output terminal, a dynamic clamping circuit for controlling a voltage difference between the first power supply and the output terminal, and a clamp selection switch electrically connected between the dynamic clamping circuit and the output terminal, and a conductive condition of the clamp selection switch is determined according to a comparison between a reference voltage and a voltage of the output terminal.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: August 3, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Osamu Souma
  • Patent number: 7768328
    Abstract: A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; a load resistance section to output a voltage according to a current output by the differential input section; differential signal output terminals to output a differential signal corresponding to the voltage output from the load resistance section; a low-pass filter to extract a direct-current component of the differential signal output from the differential signal output terminals; and a load adjustment section to feed back the direct-current component extracted by the low-pass filter to adjust a resistance value of the load resistance section.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: August 3, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yasushi Aoki
  • Patent number: 7768768
    Abstract: A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to the basic power supply wiring. Furthermore, in the cell disposition region are disposed regularly plural ordinary power switch cells that supply a first current to the primitive cell respectively. The power reinforcement cell including a power switch cell configured so as to flow a predetermined current to the high current consumption cell is disposed near the high current consumption cell.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 3, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Taro Sakurabayashi
  • Publication number: 20100187590
    Abstract: A semiconductor device includes a plurality of metal insulator semiconductor (MIS) transistors. The plurality of MIS transistors each includes a gate electrode formed above a channel region of a semiconductor substrate via a gate insulating film and source/drain regions formed on both sides of the channel region. The gate electrode is electrically connected to an interconnect via a first plug. The interconnect has a plurality of vias formed thereon. The plurality of MIS transistors have threshold voltages different from one another due to variations in quantities of electric charges trapped by the gate insulating films respectively corresponding to the plurality of MIS transistors.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 29, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Hirokazu Ishigaki
  • Patent number: 7763968
    Abstract: In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyuki Kunishima, Noriaki Oda
  • Patent number: 7763985
    Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoichiro Kurita, Rieka Ouchi, Takashi Miyazaki, Toshiyuki Yamada
  • Patent number: 7765391
    Abstract: To provide a multiprocessor system and a boot-up method of a slave system, which can reduce the number of components with simple configuration. A multiprocessor system according to an embodiment of the present invention includes a master system, and a slave system connected with the master system through an interprocessor communication interface. The master system includes a program ROM storing a boot program for the slave system. The slave system includes a loader downloading the boot program stored in the program ROM through the interprocessor communication interface.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Mariko Uemura, Kei Suda
  • Patent number: 7764085
    Abstract: A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN).
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyuki Takahashi, Hiroyuki Satake
  • Patent number: 7763516
    Abstract: A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Toshifumi Takahashi
  • Patent number: 7763812
    Abstract: A semiconductor device according to the present invention includes first through fourth internal terminals placed along the perimeter of a substrate, a circuit coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal. The circuit outputs a signal indicative of a connection state the first internal terminal and the first external terminal. A distance between centers of the first and second internal terminals is L1 in a direction parallel to one side of the substrate beside which the first external terminal is placed. A distance between centers of the third and fourth internal terminals is L2 in a direction parallel to one side of the substrate beside which the second and third external terminals are placed. The distance L1 is set smaller than the distance L2.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyoshi Fukuda
  • Patent number: 7764556
    Abstract: A semiconductor storage device according to one aspect of the present invention includes a reference voltage source connected to a capacitor of a cell included in a memory, a buffer circuit holding data to be written in the cell, and a counter noise generator outputting a counter noise current canceling a noise current generated by rewriting the data in the cell to the reference voltage source according to the data held in the buffer circuit.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 7765335
    Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tomofumi Iima
  • Patent number: 7763979
    Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 27, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Kazuhiko Endo
  • Patent number: 7764142
    Abstract: A bit phase shifter includes a plurality of phase shifters having phase shift amounts and connected in series through connection paths; and a first adjusting circuit provided in the connection path between every adjacent two of the plurality of phase shifters. The first adjusting circuit includes a first inductance which attains impedance matching to each of capacitances provided by the adjacent two phase shifters.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Miya
  • Patent number: 7764077
    Abstract: Provided are a semiconductor evaluation element capable of analytically estimating the amount of DC variation of a MOS transistor which is caused by formed contacts, and an evaluation circuit and an evaluation method using the semiconductor evaluation element. The semiconductor evaluation element such as a MOS transistor includes: a gate; diffusion layers; measurement contacts; and floating contacts. The diffusion layers are formed on both sides of the gate and serve as a source and a drain. The measurement contacts are provided in positions apart from the gate on the diffusion layers. The floating contacts are provided between the gate and the measurement contacts to connect electrically isolated metal layers with the diffusion layers.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yasuhisa Naruta
  • Patent number: 7765444
    Abstract: A failure diagnosing method of logic circuits includes generating failure candidate data for logic circuits based on failure diagnosis data obtained from the logic circuits by using a failure diagnosis tool; and inputting the failure candidate data for the logic circuits. A predetermined data is extracted from each of the failure candidate data for the logic circuits. Failures of the logic circuits are diagnosed by collecting a name of each of the failure candidate data from the predetermined data and the number of failure candidate data; and the collected data are outputted on a display unit.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: July 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masafumi Nikaido, Tomomi Ukai
  • Publication number: 20100184296
    Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 22, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Hidetaka Nambu, Nobuo Hironaga, Futoshi Ota, Toru Yokoyama, Osamu Sugawara, Ryo Satou, Masato Tamura
  • Publication number: 20100182060
    Abstract: A digital phase-locked loop circuit includes: a first counter which counts a first clock; a second counter which counts third clocks into which a second clock is divided; a first phase detector which detects a relative phase difference between the first and the third clocks according to a first comparison result that clocks in which the third clock is delayed are compared with the first clock and a second comparison result that clocks in which the first clock is delayed are compared with the third clock; a second phase detector which measures the period of the second clock; a phase error calculating unit which calculates a phase difference between the first and the third clocks according to the value that the result detected by the first phase detector is normalized by the result detected by the second phase detector and the count values of the first and the second counters; and a DCO which outputs the second clock according to the result calculated by the phase error calculating unit.
    Type: Application
    Filed: January 11, 2010
    Publication date: July 22, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Satoshi Fujino, Masafumi Watanabe
  • Publication number: 20100182029
    Abstract: An electrical testing device has a first probe that electrically contacts with an inspection device, a second probe that is electrically connected to the first probe and electrically contacts with an external terminal of a test object, a cylinder that houses the first probe and second probe, and into which and out of which a fluid flows between the first probe and second probe, and a fluid pressure regulator that controls the fluid pressure in the cylinder. The fluid pressure in the cylinder controls the contact force between the first probe and the inspection device and the contact force between the second probe and the external terminal.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 22, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kentarou SEKINO
  • Patent number: 7760571
    Abstract: An image memory is composed of a memory cell array, first and second area selecting circuits, and a write circuit. The memory cell array includes memory elements arrayed in rows and columns, each of the memory elements being adapted to store pixel data. The first area selecting circuit is adapted to select a plurality of row addresses at the same time, and the second area selecting circuit is adapted to select a plurality of column addresses at the same time. The write circuit is adapted to write same pixel data into selected memory elements out of the memory elements, the selected memory elements being associated with the selected row addresses and column addresses.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 20, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hirobumi Furihata, Junyou Shioda