Patents Assigned to NEC Electronics
-
Patent number: 7755191Abstract: A semiconductor device includes a first copper-containing conductive film formed on a substrate, insulating films formed on the first copper-containing conductive film with a concave portion reaching the first copper-containing conductive film, a second barrier insulating film formed to cover the side wall of the concave portion of these insulating films, a second adhesive alloy film made of copper and a dissimilar element other than copper, and coming in contact with the first copper-containing conductive film at the bottom surface of the concave portion and in contact with the second barrier insulating film at the side wall of the concave portion to cover the inside wall of the concave portion, and a second copper-containing conductive film containing copper as a main component, and formed on the second adhesive alloy film in contact with the second adhesive alloy film to fill the concave portion.Type: GrantFiled: March 20, 2007Date of Patent: July 13, 2010Assignee: NEC Electronics CorporationInventor: Akira Furuya
-
Patent number: 7756232Abstract: Disclosed is a clock and data recover circuit including N flip-flops (F/Fs) for sampling an input data signal using N-phase clocks, a phase comparison circuit for performing phase comparison based on outputs of the F/Fs, a filter or smoothing a result of the phase comparison and outputting an up/down signal, up/down counters, each for receiving an output of the filter and counting up or down a count value thereof, a phase shift circuit for adjustably controlling phases of the clocks for edge detection and the clocks for data sampling according to phase control signals from an up/down counter and an up/down counter, respectively, and an up/down control circuit for receiving a control signal for controlling maximum and minimum values of count values of the up/down counter, generating a signal for controlling counting up and down of the up/down counter based on the count value of the up/down counter, and supplying the generated signal to the up/down counter.Type: GrantFiled: August 28, 2006Date of Patent: July 13, 2010Assignee: NEC Electronic CorporationInventors: Yasushi Aoki, Takanori Saeki, Koichiro Kiguchi
-
Patent number: 7754543Abstract: A method of patterning a multiple-layered resist film and a method of manufacturing a semiconductor device, which can provide an improved reliability of the semiconductor devices and a reduced operation time for an etch process, are provided. A method of patterning a multiple-layered resist film according to the present invention include: forming a lower layer resist film 104 on a semiconductor substrate; forming a silicon-containing upper layer resist film on the lower layer resist film 104; patterning the silicon-containing upper layer resist film into a predetermined geometry; and performing dry etching process for removing the lower layer resist film 104 through a mask of the patterned silicon-containing upper layer resist film 106 employing an etching gas containing oxygen (O2) gas and argon (Ar) gas at a pressure within a range of from 0.075 mTorr to 50 mTorr both inclusive.Type: GrantFiled: December 14, 2006Date of Patent: July 13, 2010Assignee: NEC Electronics CorporationInventor: Eiichi Soda
-
Publication number: 20100175034Abstract: A layout verification device according to the present invention includes a layout verification unit that outputs a first error graphic corresponding to an area where there is an inconsistency with a design rule in a first layout pattern, and includes a target error graphic setting unit that sets a processing target area including the first error graphic, an error graphic search unit that searches a second error graphic included in a processing target area of a second layout pattern where verification by the layout verification unit has already been performed, and an error graphic equivalence judgment unit that judges that the first error graphic and the second error graphic are non-equivalent when a second target vertex coordinate of the second error graphic does not match any one of a plurality of peripheral vertex coordinates set in grid intersections adjacent to the first target vertex coordinate of the first error graphic.Type: ApplicationFiled: January 4, 2010Publication date: July 8, 2010Applicant: NEC Electronics CorporationInventor: Taketoshi Tsurumoto
-
Publication number: 20100171517Abstract: An impedance measurement method for circuits that has multiple power supply ports and a common ground shared by the multiple power supply ports, that includes finding multiple mutual impedances; finding approximate values for the ground impedance from the multiple mutual impedances; calculating multiple power supply port impedances from the approximate ground impedance values; and generating an equivalent circuit for the applicable circuit based on the ground impedances.Type: ApplicationFiled: January 5, 2010Publication date: July 8, 2010Applicant: NEC Electronics CorporationInventor: Ryuichi Oikawa
-
Patent number: 7750612Abstract: A voltage-pulse converting circuit according to an embodiment of the invention includes: a first input terminal and a second input terminal applied with an input voltage to be converted into a pulse; an integrator having positive and negative input terminals; an input switching unit switching connection between the first and second input terminal and the positive and negative input terminals of the integrator; and a first comparator comparing a first detection voltage with an output voltage of the integrator and a second comparator comparing a second detection voltage different from the first detection voltage with the output voltage, the input switching unit switching the connection based on a comparison result of the first and second comparators.Type: GrantFiled: November 20, 2006Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventor: Kouji Yokosawa
-
Patent number: 7752467Abstract: The integrated circuit device includes a CPU having an arithmetic circuit and a Power Management Unit implementing power control of the CPU through a power IC. The Power Management Unit has no arithmetic circuit. The Power Management Unit includes RAM storing a plurality of commands and a control section implementing power control of the CPU according to the commands stored in the RAM.Type: GrantFiled: October 4, 2005Date of Patent: July 6, 2010Assignee: Nec Electronics CorporationInventor: Tatsuya Tokue
-
Patent number: 7750665Abstract: A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the internal circuit, a feedback line branched off from signal line in buffer transmitting data signal to an output stage circuit of the output buffer, and a delay test circuit connected to the feedback line.Type: GrantFiled: March 17, 2008Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventors: You Miyazaki, Mamoru Konno
-
Patent number: 7750765Abstract: A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.Type: GrantFiled: October 10, 2008Date of Patent: July 6, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Taras Kushta, Kaoru Narita, Takanori Saeki, Tomoyuki Kaneko, Hirokazu Tohya
-
Patent number: 7750402Abstract: In a power semiconductor device including a semiconductor substrate of a first conductivity type, a source region of a second conductivity type formed in a surface portion of the semiconductor substrate, and a drain drift region of the second conductivity type formed in the surface portion of the semiconductor substrate, the drain drift region being apart from the source region, a drain region of the second conductivity type is formed in a surface portion of the drain drift region. The drain region has a larger impurity concentration than the drain drift region. A drain buried region of the second conductivity type is formed immediately below the drain region in the drain drift region. The drain buried region has a larger impurity diffusion region than the drain drift region. A gate insulating layer is formed on the semiconductor substrate between the source region and the drain drift region, and a gate electrode is formed on the gate insulating layer.Type: GrantFiled: August 25, 2004Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventor: Kenya Kobayashi
-
Patent number: 7752420Abstract: Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15) based on a layout information indicating signal Pout whose timing has been adjusted.Type: GrantFiled: February 13, 2008Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventors: Yoshitaka Izawa, Yoshikazu Yabe
-
Patent number: 7750730Abstract: A semiconductor integrated circuit device provided with an input terminal supplied with a reference frequency signal from outside of the device, a bandpass filter circuit coupled to the input terminal and outputting an internal reference frequency signal and a PLL circuit coupled to the bandpass filter circuit to receive the internal reference frequency signal. The input terminal is supplied with the reference frequency signal generated by a quartz oscillator or the like mounted on the exterior of the semiconductor integrated circuit device. In response to the signal supplied to the input terminal, the bandpass filter circuit restricts components in a bandwidth except for the frequency of the reference frequency signal, and thus supplies the reference signal to the PLL circuit. The PLL circuit operates by using the reference frequency signal as the reference signal.Type: GrantFiled: October 24, 2007Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Irino
-
Patent number: 7752516Abstract: A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates an output clock signal from the first separation clock signal and a first scan clock signal to the test circuit. A second scan clock signal is supplied to the test circuit.Type: GrantFiled: March 29, 2006Date of Patent: July 6, 2010Assignee: NEC Electronics CorporationInventor: Yoshiaki Sera
-
Patent number: 7746141Abstract: A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set.Type: GrantFiled: June 7, 2007Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Hiroyuki Takahashi
-
Patent number: 7745736Abstract: An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.Type: GrantFiled: January 30, 2006Date of Patent: June 29, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Kenta Ogawa, Jun Tsukano, Takehiko Maeda, Tadanori Shimoto, Shintaro Yamamichi, Kazuhiro Baba
-
Patent number: 7745937Abstract: A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of starting the silicon processing step (depressurizing step). Thereafter, a second gas including a nitrogen-containing compound is introduced into the vacuum chamber, and the semiconductor substrate is irradiated with the second gas plasma (nitrogen plasma step).Type: GrantFiled: February 16, 2006Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventors: Tatsuya Usami, Koichi Ohto, Toshiyuki Takewaki
-
Patent number: 7746161Abstract: A semiconductor device includes a first voltage generator which outputs a first signal to a first node, a second voltage generator which outputs a second signal to a second node, a capacitor coupled between the first and second nodes; and a current supply circuit coupled to said second node. While the first voltage generator outputs the first signal to set the first node to a first voltage potential, the second voltage generator is activated to output the second signal to set the second node to a second voltage potential. At that time, the capacitor influences to the second node, based on a coupling capacitance thereof and the current supplying circuit supplies a current to suppress the influence.Type: GrantFiled: November 13, 2007Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Toshiharu Okamoto
-
Patent number: 7745936Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.Type: GrantFiled: June 30, 2008Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Mitani
-
Publication number: 20100159673Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: NEC Electronics CorporationInventor: Takehiro Ueda
-
Patent number: 7741894Abstract: An output circuit having an output transistor which switches a load current is disclosed. The output circuit includes a load current detecting block which detects a current level of the load current, and a slew rate adjustment block which adjusts a slew rate during a turn-off transition of the output transistor in response to a result of the detection by the load current detecting block.Type: GrantFiled: September 24, 2004Date of Patent: June 22, 2010Assignee: NEC Electronics CorporationInventor: Masaki Kojima